[PATCH] D70858: [GlobalISel][RFC] Importing insert/extract vector element patterns

[Petar Avramovic via Phabricator via llvm-commits]

Petar.Avramovic updated this revision to Diff 239141.
Petar.Avramovic added a comment.

Rebase and update.

Enforce same type of vector scalar and elt scalar in MachineVerifier for G_INSERT_VECTOR_ELT and G_EXTRACT_VECTOR_ELT.
Introducing two new similar opcodes without type constraint G_INSERT_VECTOR_ELT_TRUNC and G_ANYEXT_EXTRACT_VECTOR_ELT.
These opcodes have no corresponding llvm-IR opcodes and targets that have extending vector extract and truncating vector insert can generate them from G_INSERT_VECTOR_ELT and G_EXTRACT_VECTOR_ELT using minVectorInsOrExtScalar (minScalar respects MachineVerifier constraints for G_INSERT_VECTOR_ELT and G_EXTRACT_VECTOR_ELT).
Mips has only sign and zero extending vector extracts thus G_ANYEXT_EXTRACT_VECTOR_ELT is not selectable and is replaced with default extending vector extract instruction G_SEXT_EXTRACT_VECTOR_ELT in custom legalize.
Updated tests.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D70858/new/

https://reviews.llvm.org/D70858

Files:
  llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
  llvm/include/llvm/CodeGen/GlobalISel/InstructionSelector.h
  llvm/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h
  llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
  llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
  llvm/include/llvm/Support/TargetOpcodes.def
  llvm/include/llvm/Target/GenericOpcodes.td
  llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
  llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
  llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
  llvm/lib/CodeGen/GlobalISel/LegalizerInfo.cpp
  llvm/lib/CodeGen/MachineVerifier.cpp
  llvm/lib/Target/Mips/MipsLegalizerInfo.cpp
  llvm/lib/Target/Mips/MipsMSAInstrInfo.td
  llvm/lib/Target/Mips/MipsPreLegalizerCombiner.cpp
  llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp
  llvm/lib/Target/Mips/MipsRegisterBanks.td
  llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
  llvm/test/CodeGen/Mips/GlobalISel/instruction-select/extract_vector_elt_imm_index.mir
  llvm/test/CodeGen/Mips/GlobalISel/instruction-select/extract_vector_elt_variable_index.mir
  llvm/test/CodeGen/Mips/GlobalISel/instruction-select/insert_vector_elt_imm_index.mir
  llvm/test/CodeGen/Mips/GlobalISel/instruction-select/insert_vector_elt_variable_index.mir
  llvm/test/CodeGen/Mips/GlobalISel/legalizer/extract_vector_elt_pre_isel.mir
  llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/extract_vector_elt_pre_isel.ll
  llvm/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/extract_vector_elt_pre_isel.mir
  llvm/test/CodeGen/Mips/GlobalISel/regbankselect/extract_vector_elt_pre_isel.mir
  llvm/unittests/CodeGen/GlobalISel/LegalizerInfoTest.cpp
  llvm/utils/TableGen/CodeGenRegisters.cpp
  llvm/utils/TableGen/GlobalISelEmitter.cpp

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