[llvm] f3e73e8 - [ARM, MVE] Fix confusing MC names for MVE VMINA/VMAXA insns.

Simon Tatham via llvm-commits llvm-commits at lists.llvm.org
Mon Jan 20 05:26:15 PST 2020


Author: Simon Tatham
Date: 2020-01-20T13:25:52Z
New Revision: f3e73e88fdd63e3342977873a5f2c3f870a2497a

URL: https://github.com/llvm/llvm-project/commit/f3e73e88fdd63e3342977873a5f2c3f870a2497a
DIFF: https://github.com/llvm/llvm-project/commit/f3e73e88fdd63e3342977873a5f2c3f870a2497a.diff

LOG: [ARM,MVE] Fix confusing MC names for MVE VMINA/VMAXA insns.

Summary:
A recent commit accidentally defined names like `MVE_VMAXAs8` as
instances of the multiclass `MVE_VMINA`, and vice versa. This has no
effect on the test suite, because nothing directly refers to those
instruction names (the isel patterns are generated in Tablegen using
`!cast<Instruction>(NAME)` inside a lower-level multiclass). But it
means that `llvm-mc -show-inst` was listing VMAXA as VMINA, and it
would also affect any further draft code gen patches that use those
instruction ids.

Reviewers: MarkMurrayARM, dmgreen, miyuki, ostannard

Reviewed By: dmgreen

Subscribers: kristof.beyls, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D73034

Added: 
    

Modified: 
    llvm/lib/Target/ARM/ARMInstrMVE.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/ARM/ARMInstrMVE.td b/llvm/lib/Target/ARM/ARMInstrMVE.td
index c26af8b3f659..70f1d75bc439 100644
--- a/llvm/lib/Target/ARM/ARMInstrMVE.td
+++ b/llvm/lib/Target/ARM/ARMInstrMVE.td
@@ -2312,16 +2312,16 @@ multiclass MVE_VMINMAXA_m<string iname, MVEVectorVTInfo VTI,
 multiclass MVE_VMINA<MVEVectorVTInfo VTI>
   : MVE_VMINMAXA_m<"vmina", VTI, umin, int_arm_mve_vmina_predicated, 0b1>;
 
-defm MVE_VMAXAs8  : MVE_VMINA<MVE_v16s8>;
-defm MVE_VMAXAs16 : MVE_VMINA<MVE_v8s16>;
-defm MVE_VMAXAs32 : MVE_VMINA<MVE_v4s32>;
+defm MVE_VMINAs8  : MVE_VMINA<MVE_v16s8>;
+defm MVE_VMINAs16 : MVE_VMINA<MVE_v8s16>;
+defm MVE_VMINAs32 : MVE_VMINA<MVE_v4s32>;
 
 multiclass MVE_VMAXA<MVEVectorVTInfo VTI>
   : MVE_VMINMAXA_m<"vmaxa", VTI, umax, int_arm_mve_vmaxa_predicated, 0b0>;
 
-defm MVE_VMINAs8  : MVE_VMAXA<MVE_v16s8>;
-defm MVE_VMINAs16 : MVE_VMAXA<MVE_v8s16>;
-defm MVE_VMINAs32 : MVE_VMAXA<MVE_v4s32>;
+defm MVE_VMAXAs8  : MVE_VMAXA<MVE_v16s8>;
+defm MVE_VMAXAs16 : MVE_VMAXA<MVE_v8s16>;
+defm MVE_VMAXAs32 : MVE_VMAXA<MVE_v4s32>;
 
 // end of MVE Integer instructions
 


        


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