[llvm] 60aed6a - [Hexagon] Add prev65 subtarget feature
Krzysztof Parzyszek via llvm-commits
llvm-commits at lists.llvm.org
Fri Jan 17 07:27:47 PST 2020
Author: Krzysztof Parzyszek
Date: 2020-01-17T09:27:27-06:00
New Revision: 60aed6a4e5d936b87f5bed0c983be0bab55b1355
URL: https://github.com/llvm/llvm-project/commit/60aed6a4e5d936b87f5bed0c983be0bab55b1355
DIFF: https://github.com/llvm/llvm-project/commit/60aed6a4e5d936b87f5bed0c983be0bab55b1355.diff
LOG: [Hexagon] Add prev65 subtarget feature
There was a change to trap1 instruction between v62 and v65. This
feature will allow the assembler/disassembler to handle different
variants depending on the CPU version.
Added:
Modified:
llvm/lib/Target/Hexagon/Hexagon.td
llvm/lib/Target/Hexagon/HexagonDepInstrInfo.td
llvm/lib/Target/Hexagon/HexagonSubtarget.h
llvm/test/MC/Hexagon/J2_trap1_dep.s
Removed:
################################################################################
diff --git a/llvm/lib/Target/Hexagon/Hexagon.td b/llvm/lib/Target/Hexagon/Hexagon.td
index fbae2758d2b1..284b839fb57b 100644
--- a/llvm/lib/Target/Hexagon/Hexagon.td
+++ b/llvm/lib/Target/Hexagon/Hexagon.td
@@ -52,6 +52,8 @@ def FeatureCompound: SubtargetFeature<"compound", "UseCompound", "true",
"Use compound instructions">;
def FeaturePackets: SubtargetFeature<"packets", "UsePackets", "true",
"Support for instruction packets">;
+def FeatureHasPreV65: SubtargetFeature<"prev65", "HasPreV65", "true",
+ "Support features deprecated in v65">;
def FeatureLongCalls: SubtargetFeature<"long-calls", "UseLongCalls", "true",
"Use constant-extended calls">;
def FeatureMemNoShuf: SubtargetFeature<"mem_noshuf", "HasMemNoShuf", "false",
@@ -94,6 +96,8 @@ def UseHVXV66 : Predicate<"HST->useHVXOps()">,
def UseZReg : Predicate<"HST->useZRegOps()">,
AssemblerPredicate<"ExtensionZReg">;
def UseCompound : Predicate<"HST->useCompound()">;
+def HasPreV65 : Predicate<"HST->hasPreV65()">,
+ AssemblerPredicate<"FeatureHasPreV65">;
def Hvx64: HwMode<"+hvx-length64b">;
def Hvx128: HwMode<"+hvx-length128b">;
@@ -102,6 +106,7 @@ def Hvx128: HwMode<"+hvx-length128b">;
// Classes used for relation maps.
//===----------------------------------------------------------------------===//
+// The classes below should remain in hierarchical order...
class ImmRegShl;
// ImmRegRel - Filter class used to relate instructions having reg-reg form
// with their reg-imm counterparts.
@@ -109,17 +114,14 @@ class ImmRegRel;
// PredRel - Filter class used to relate non-predicated instructions with their
// predicated forms.
class PredRel;
-// PredNewRel - Filter class used to relate predicated instructions with their
-// predicate-new forms.
class PredNewRel: PredRel;
// NewValueRel - Filter class used to relate regular store instructions with
// their new-value store form.
class NewValueRel: PredNewRel;
-// NewValueRel - Filter class used to relate load/store instructions having
-//
diff erent addressing modes with each other.
class AddrModeRel: NewValueRel;
class PostInc_BaseImm;
class IntrinsicsRel;
+// ... through here.
//===----------------------------------------------------------------------===//
// Generate mapping table to relate non-predicate instructions with their
@@ -338,24 +340,24 @@ class Proc<string Name, SchedMachineModel Model,
def : Proc<"generic", HexagonModelV60,
[ArchV5, ArchV55, ArchV60,
- FeatureCompound, FeatureDuplex, FeatureMemops, FeatureNVJ,
- FeatureNVS, FeaturePackets, FeatureSmallData]>;
+ FeatureCompound, FeatureDuplex, FeatureHasPreV65, FeatureMemops,
+ FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData]>;
def : Proc<"hexagonv5", HexagonModelV5,
[ArchV5,
- FeatureCompound, FeatureDuplex, FeatureMemops, FeatureNVJ,
- FeatureNVS, FeaturePackets, FeatureSmallData]>;
+ FeatureCompound, FeatureDuplex, FeatureHasPreV65, FeatureMemops,
+ FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData]>;
def : Proc<"hexagonv55", HexagonModelV55,
[ArchV5, ArchV55,
- FeatureCompound, FeatureDuplex, FeatureMemops, FeatureNVJ,
- FeatureNVS, FeaturePackets, FeatureSmallData]>;
+ FeatureCompound, FeatureDuplex, FeatureHasPreV65, FeatureMemops,
+ FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData]>;
def : Proc<"hexagonv60", HexagonModelV60,
[ArchV5, ArchV55, ArchV60,
- FeatureCompound, FeatureDuplex, FeatureMemops, FeatureNVJ,
- FeatureNVS, FeaturePackets, FeatureSmallData]>;
+ FeatureCompound, FeatureDuplex, FeatureHasPreV65, FeatureMemops,
+ FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData]>;
def : Proc<"hexagonv62", HexagonModelV62,
[ArchV5, ArchV55, ArchV60, ArchV62,
- FeatureCompound, FeatureDuplex, FeatureMemops, FeatureNVJ,
- FeatureNVS, FeaturePackets, FeatureSmallData]>;
+ FeatureCompound, FeatureDuplex, FeatureHasPreV65, FeatureMemops,
+ FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData]>;
def : Proc<"hexagonv65", HexagonModelV65,
[ArchV5, ArchV55, ArchV60, ArchV62, ArchV65,
FeatureCompound, FeatureDuplex, FeatureMemNoShuf, FeatureMemops,
diff --git a/llvm/lib/Target/Hexagon/HexagonDepInstrInfo.td b/llvm/lib/Target/Hexagon/HexagonDepInstrInfo.td
index 9053f3b4788f..f0cee253d12b 100644
--- a/llvm/lib/Target/Hexagon/HexagonDepInstrInfo.td
+++ b/llvm/lib/Target/Hexagon/HexagonDepInstrInfo.td
@@ -5709,7 +5709,7 @@ def J2_trap1 : HInst<
(outs IntRegs:$Rx32),
(ins IntRegs:$Rx32in, u8_0Imm:$Ii),
"trap1($Rx32,#$Ii)",
-tc_b9e09e03, TypeJ>, Enc_33f8ba {
+tc_b9e09e03, TypeJ>, Enc_33f8ba, Requires<[HasV65]> {
let Inst{1-0} = 0b00;
let Inst{7-5} = 0b000;
let Inst{13-13} = 0b0;
@@ -5726,7 +5726,7 @@ def J2_trap1_noregmap : HInst<
(outs),
(ins u8_0Imm:$Ii),
"trap1(#$Ii)",
-tc_b9e09e03, TypeMAPPING> {
+tc_b9e09e03, TypeMAPPING>, Requires<[HasV65]> {
let hasSideEffects = 1;
let isPseudo = 1;
let isCodeGenOnly = 1;
@@ -17876,6 +17876,17 @@ let opExtentBits = 18;
let opExtentAlign = 2;
let opNewValue = 1;
}
+def PS_trap1 : HInst<
+(outs),
+(ins u8_0Imm:$Ii),
+"trap1(#$Ii)",
+tc_b9e09e03, TypeJ>, Enc_a51a9a, Requires<[HasPreV65]> {
+let Inst{1-0} = 0b00;
+let Inst{7-5} = 0b000;
+let Inst{13-13} = 0b0;
+let Inst{31-16} = 0b0101010010000000;
+let isSolo = 1;
+}
def S2_addasl_rrri : HInst<
(outs IntRegs:$Rd32),
(ins IntRegs:$Rt32, IntRegs:$Rs32, u3_0Imm:$Ii),
diff --git a/llvm/lib/Target/Hexagon/HexagonSubtarget.h b/llvm/lib/Target/Hexagon/HexagonSubtarget.h
index 8787c9b263fb..27606337c615 100644
--- a/llvm/lib/Target/Hexagon/HexagonSubtarget.h
+++ b/llvm/lib/Target/Hexagon/HexagonSubtarget.h
@@ -54,6 +54,7 @@ class HexagonSubtarget : public HexagonGenSubtargetInfo {
bool UseSmallData = false;
bool UseZRegOps = false;
+ bool HasPreV65 = false;
bool HasMemNoShuf = false;
bool EnableDuplex = false;
bool ReservedR19 = false;
diff --git a/llvm/test/MC/Hexagon/J2_trap1_dep.s b/llvm/test/MC/Hexagon/J2_trap1_dep.s
index 1fd141fe79e6..8beb55598f08 100644
--- a/llvm/test/MC/Hexagon/J2_trap1_dep.s
+++ b/llvm/test/MC/Hexagon/J2_trap1_dep.s
@@ -1,6 +1,6 @@
-# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv62 -filetype=obj %s | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-V62
-# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv65 -filetype=obj %s | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-V65
+# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv62 -filetype=obj %s | llvm-objdump -mcpu=hexagonv62 -d - | FileCheck %s --check-prefix=CHECK-V62
+# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv65 -filetype=obj %s | llvm-objdump -mcpu=hexagonv65 -d - | FileCheck %s --check-prefix=CHECK-V65
-# CHECK-V62: trap1(r0,#0)
+# CHECK-V62: trap1(#0)
# CHECK-V65: trap1(r0,#0)
trap1(#0)
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