[PATCH] D71773: [AArch64][SVE] Update the definition of AdvSIMD_GatherLoad_VecTorBase_Intrinsic

[Andrzej Warzynski via Phabricator via llvm-commits]

andwar updated this revision to Diff 238744.
andwar added a comment.

Revert previous patch and settle on `llvm.aarch64.sve.ld1.gather.scalar.offset`

Based on the overall feedback, `llvm.aarch64.sve.ld1.gather.scalar.offset` feels sufficient to cover all cases:

- For "vector base, scalar index" ACLE intrinisics we will have to do the scaling in clang. It is then mapped to `GLD1_IMM` provided that the index is within the supported range.
- For "vector base, scalar offset" we have 1:1 mapping between the ACLE and IR intrinsic and then in DAG Combine we map it to either `GLD1` or `GLD1_UXTW`
- For "vector base, scalar index" ACLE intriniscs where the index is out-of-range, we fall-back to "vector base, scalar offset"

I've kept the changes for scatter stores.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D71773/new/

https://reviews.llvm.org/D71773

Files:
  llvm/include/llvm/IR/IntrinsicsAArch64.td
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/test/CodeGen/AArch64/sve-gather-scatter-dag-combine.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-gather-loads-vector-base-imm-offset.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-gather-loads-vector-base-scalar-offset.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-gather-loads-vector-base.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-scatter-stores-vector-base-imm-offset.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-scatter-stores-vector-base-scalar-offset.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-scatter-stores-vector-base.ll

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