[PATCH] D72771: TableGen: Work around assert on Mips register definitions

[Simon Atanasyan via Phabricator via llvm-commits]

atanasyan accepted this revision.
atanasyan added a comment.
This revision is now accepted and ready to land.

LGTM

I'll take a look on MIPS vector register definitions. Four register classes looks really ill formed.


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https://reviews.llvm.org/D72771