[PATCH] D71216: [AArch64] Implement passing SVE vectors by ref for AAPCS.

[Eli Friedman via Phabricator via llvm-commits]

efriedma accepted this revision.
efriedma added a comment.

Please add a comment explaining each `isScalableVector()`, to make it clear why we're excluding them. Otherwise LGTM



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Comment at: llvm/test/CodeGen/AArch64/sve-calling-convention-byref.ll:9
+;      x1 = &%z9
+define aarch64_sve_vector_pcs <vscale x 4 x i32> @callee_with_many_sve_arg(<vscale x 4 x i32> %z0, <vscale x 4 x i32> %z1, <vscale x 4 x i32> %z2, <vscale x 4 x i32> %z3, <vscale x 4 x i32> %z4, <vscale x 4 x i32> %z5, <vscale x 4 x i32> %z6, <vscale x 4 x i32> %z7, <vscale x 4 x i32> %z8, <vscale x 4 x i32> %z9) {
+; CHECK: name: callee_with_many_sve_arg
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I just thought of this, but should scalable arguments be allowed for calls using the regular C calling convetion?  If they are, do we need any additional changes to make that work?


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https://reviews.llvm.org/D71216