[PATCH] D72629: [ARM][MVE] Disallow VPSEL for tail predication

[Sam Parker via Phabricator via llvm-commits]

samparker created this revision.
samparker added reviewers: dmgreen, SjoerdMeijer.
Herald added subscribers: hiraditya, kristof.beyls.
Herald added a project: LLVM.
samparker added parent revisions: D72509: [ARM][LowOverheadLoops] Allow all MVE instrs., D72504: [ARM][LowOverheadLoops] Change predicate inspection.

Due to the current way that we collect predicated instructions, we can't easily handle vpsel in tail predicated loops. There are a couple of issues:

1. It will use the VPR as a predicate operand, but doesn't have to be instead a VPT block, which means we can assert while building up the VPT block because we don't find another VPST to being a new one.
2. VPSEL still requires a VPR operand even after tail predicating, which means we can't remove it unless there is another instruction, such as vcmp, that can provide the VPR def.

The first issue should be a relatively simple fix in the logic of the LowOverheadLoops pass, whereas the second will require us to represent the 'implicit' tail predication with an explicit value.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D72629

Files:
  llvm/lib/Target/ARM/ARMInstrMVE.td
  llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpnot-1.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpnot-2.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpnot-3.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpsel-1.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpsel-2.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpsel-3.mir

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