[PATCH] D72573: [SelectionDAG] ComputeKnownBits - minimum leading/trailing zero bits in LSHR/SHL (PR44526)

[Roman Lebedev via llvm-commits]

Thanks!

On Mon, Jan 13, 2020 at 5:44 PM Simon Pilgrim via Phabricator
<reviews at reviews.llvm.org> wrote:
>
> RKSimon marked 2 inline comments as done.
> RKSimon added inline comments.
>
>
> ================
> Comment at: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:2837
>        Known.Zero.setLowBits(Shift);
> +    } else {
> +      // No matter the shift amount, the trailing zeros will stay zero.
> ----------------
> lebedev.ri wrote:
> > Could also have `getValidMinimumShiftAmountConstant()` branch like for `ISD::SRL`?
> Done in a number of follow up commits.
>
>
> ================
> Comment at: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:2870-2871
>        Known.One.ashrInPlace(Shift);
>      }
>      break;
>    case ISD::FSHL:
> ----------------
> lebedev.ri wrote:
> > RKSimon wrote:
> > > lebedev.ri wrote:
> > > > Same for signbit given arithmetic right-shift?
> > > ComputeNumSignBits already does something similar for ISA::SRA - it always gets the number of sign bits of Op0 and increases it if the shift amount is constant
> > Ah indeed, but then `ComputeNumSignBits()` doesn't handle `ISD::SRL` like it does `ISA::SRA`.
> Yup, ISD::SRL ComputeNumSignBits() calls use the default fallback to call ComputeKnownBits() as we're only interested in leading zero bits anyway.
>
>
> Repository:
>   rG LLVM Github Monorepo
>
> CHANGES SINCE LAST ACTION
>   https://reviews.llvm.org/D72573/new/
>
> https://reviews.llvm.org/D72573
>
>
>