[PATCH] D68203: Add support for (expressing) vscale.

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen updated this revision to Diff 237652.
sdesmalen marked 5 inline comments as done.
sdesmalen added a comment.

- Simplified the llvm.vscale intrinsic to no longer take the scaling argument. This means the scaling is left to an explicit `mul` which has explicit wrapping flags. This in turn simplifies the code in SelectionDAG for merging the multiplier into the VSCALE ISD node (this should only happen when it is known that no wrapping occurs).
- Also made llvm.vscale overloadable, so that it can return vscale in different types.
- Added special patterns for `mul vscale, 1` and `mul vscale, -1`.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D68203/new/

https://reviews.llvm.org/D68203

Files:
  llvm/docs/LangRef.rst
  llvm/include/llvm/CodeGen/ISDOpcodes.h
  llvm/include/llvm/CodeGen/SelectionDAG.h
  llvm/include/llvm/IR/Intrinsics.td
  llvm/include/llvm/IR/PatternMatch.h
  llvm/include/llvm/Target/TargetSelectionDAG.td
  llvm/lib/Analysis/ConstantFolding.cpp
  llvm/lib/CodeGen/CodeGenPrepare.cpp
  llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
  llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
  llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
  llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/test/CodeGen/AArch64/sve-vscale.ll

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