[PATCH] D72573: [SelectionDAG] ComputeKnownBits - minimum leading/trailing zero bits in LSHR/SHL (PR44526)

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri accepted this revision.
lebedev.ri added a comment.
This revision is now accepted and ready to land.

LG, thank you.



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Comment at: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:2837
       Known.Zero.setLowBits(Shift);
+    } else {
+      // No matter the shift amount, the trailing zeros will stay zero.
----------------
Could also have `getValidMinimumShiftAmountConstant()` branch like for `ISD::SRL`?


================
Comment at: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:2870-2871
       Known.One.ashrInPlace(Shift);
     }
     break;
   case ISD::FSHL:
----------------
RKSimon wrote:
> lebedev.ri wrote:
> > Same for signbit given arithmetic right-shift?
> ComputeNumSignBits already does something similar for ISA::SRA - it always gets the number of sign bits of Op0 and increases it if the shift amount is constant
Ah indeed, but then `ComputeNumSignBits()` doesn't handle `ISD::SRL` like it does `ISA::SRA`.


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  https://reviews.llvm.org/D72573/new/

https://reviews.llvm.org/D72573