[PATCH] D72570: [PowerPC][Future] Prefixed Instructions 64 Byte Boundary Support

[Stefan Pintilie via Phabricator via llvm-commits]

stefanp created this revision.
stefanp added reviewers: power-llvm-team, nemanjai, hfinkel.
Herald added subscribers: shchenz, jsji, kbarton, hiraditya, mgorny.
Herald added a project: LLVM.
stefanp added a parent revision: D72569: [PowerPC][Future] Add prefixed instruction paddi to future CPU.
Herald added a subscriber: wuzish.

A known limitation for Future CPU is that the new prefixed instructions may not cross 64 Byte boundaries.
All instructions are already 4 byte aligned so the only situation where this can occur is when the prefix is in one 64 byte block and the instruction that is prefixed is at the top of the next 64 byte block. To fix this case `PPCELFStreamer` was added to intercept `EmitInstruction`. When a prefixed instruction is emitted we try to align it to 64 Bytes by adding a maximum of 4 bytes. If the prefixed instruction crosses the 64 Byte boundary then the alignment would trigger and a 4 byte nop would be added to push the instruction into the next 64 byte block.


https://reviews.llvm.org/D72570

Files:
  llvm/lib/Target/PowerPC/MCTargetDesc/CMakeLists.txt
  llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFStreamer.cpp
  llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFStreamer.h
  llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
  llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.h
  llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp
  llvm/lib/Target/PowerPC/PPCInstrInfo.h
  llvm/test/MC/PowerPC/ppc64-prefix-align-labels.s
  llvm/test/MC/PowerPC/ppc64-prefix-align.s

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