[llvm] a9052b4 - [AArch64] Add isAuthenticated predicate to MCInstDesc
Vedant Kumar via llvm-commits
llvm-commits at lists.llvm.org
Fri Jan 10 14:31:03 PST 2020
Author: Vedant Kumar
Date: 2020-01-10T14:30:52-08:00
New Revision: a9052b4dfc1b25bd58480668d221365495fa9101
URL: https://github.com/llvm/llvm-project/commit/a9052b4dfc1b25bd58480668d221365495fa9101
DIFF: https://github.com/llvm/llvm-project/commit/a9052b4dfc1b25bd58480668d221365495fa9101.diff
LOG: [AArch64] Add isAuthenticated predicate to MCInstDesc
Add a predicate to MCInstDesc that allows tools to determine whether an
instruction authenticates a pointer. This can be used by diagnostic
tools to hint at pointer authentication failures.
Differential Revision: https://reviews.llvm.org/D70329
rdar://55089604
Added:
Modified:
llvm/include/llvm/MC/MCInstrDesc.h
llvm/include/llvm/Target/Target.td
llvm/lib/Target/AArch64/AArch64InstrFormats.td
llvm/lib/Target/AArch64/AArch64InstrInfo.td
llvm/unittests/Target/AArch64/InstSizes.cpp
llvm/utils/TableGen/CodeGenInstruction.cpp
llvm/utils/TableGen/CodeGenInstruction.h
llvm/utils/TableGen/InstrDocsEmitter.cpp
llvm/utils/TableGen/InstrInfoEmitter.cpp
Removed:
################################################################################
diff --git a/llvm/include/llvm/MC/MCInstrDesc.h b/llvm/include/llvm/MC/MCInstrDesc.h
index e6af40868c30..506f2c09304c 100644
--- a/llvm/include/llvm/MC/MCInstrDesc.h
+++ b/llvm/include/llvm/MC/MCInstrDesc.h
@@ -176,6 +176,7 @@ enum Flag {
Add,
Trap,
VariadicOpsAreDefs,
+ Authenticated,
};
}
@@ -416,6 +417,15 @@ class MCInstrDesc {
return Flags & (1ULL << MCID::VariadicOpsAreDefs);
}
+ /// Return true if this instruction authenticates a pointer (e.g. LDRAx/BRAx
+ /// from ARMv8.3, which perform loads/branches with authentication).
+ ///
+ /// An authenticated instruction may fail in an ABI-defined manner when
+ /// operating on an invalid signed pointer.
+ bool isAuthenticated() const {
+ return Flags & (1ULL << MCID::Authenticated);
+ }
+
//===--------------------------------------------------------------------===//
// Side Effect Analysis
//===--------------------------------------------------------------------===//
diff --git a/llvm/include/llvm/Target/Target.td b/llvm/include/llvm/Target/Target.td
index 321655d06b8e..b122b51bb169 100644
--- a/llvm/include/llvm/Target/Target.td
+++ b/llvm/include/llvm/Target/Target.td
@@ -530,6 +530,7 @@ class Instruction : InstructionEncoding {
bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains?
bit isNotDuplicable = 0; // Is it unsafe to duplicate this instruction?
bit isConvergent = 0; // Is this instruction convergent?
+ bit isAuthenticated = 0; // Does this instruction authenticate a pointer?
bit isAsCheapAsAMove = 0; // As cheap (or cheaper) than a move instruction.
bit hasExtraSrcRegAllocReq = 0; // Sources have special regalloc requirement?
bit hasExtraDefRegAllocReq = 0; // Defs have special regalloc requirement?
diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
index e9cacbf739ef..b22fc160d5d4 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -1483,6 +1483,7 @@ class RCPCLoad<bits<2> sz, string asm, RegisterClass RC>
class AuthBase<bits<1> M, dag oops, dag iops, string asm, string operands,
list<dag> pattern>
: I<oops, iops, asm, operands, "", pattern>, Sched<[]> {
+ let isAuthenticated = 1;
let Inst{31-25} = 0b1101011;
let Inst{20-11} = 0b1111100001;
let Inst{10} = M;
@@ -1522,6 +1523,7 @@ class BaseAuthLoad<bit M, bit W, dag oops, dag iops, string asm,
bits<10> offset;
bits<5> Rn;
bits<5> Rt;
+ let isAuthenticated = 1;
let Inst{31-24} = 0b11111000;
let Inst{23} = M;
let Inst{22} = offset{9};
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index f4d340c9f06a..1fff8d78af0f 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -819,20 +819,26 @@ let Predicates = [HasComplxNum, HasNEON] in {
let Uses = [LR], Defs = [LR] in {
def PACIAZ : SystemNoOperands<0b000, "paciaz">;
def PACIBZ : SystemNoOperands<0b010, "pacibz">;
- def AUTIAZ : SystemNoOperands<0b100, "autiaz">;
- def AUTIBZ : SystemNoOperands<0b110, "autibz">;
+ let isAuthenticated = 1 in {
+ def AUTIAZ : SystemNoOperands<0b100, "autiaz">;
+ def AUTIBZ : SystemNoOperands<0b110, "autibz">;
+ }
}
let Uses = [LR, SP], Defs = [LR] in {
def PACIASP : SystemNoOperands<0b001, "paciasp">;
def PACIBSP : SystemNoOperands<0b011, "pacibsp">;
- def AUTIASP : SystemNoOperands<0b101, "autiasp">;
- def AUTIBSP : SystemNoOperands<0b111, "autibsp">;
+ let isAuthenticated = 1 in {
+ def AUTIASP : SystemNoOperands<0b101, "autiasp">;
+ def AUTIBSP : SystemNoOperands<0b111, "autibsp">;
+ }
}
let Uses = [X16, X17], Defs = [X17], CRm = 0b0001 in {
def PACIA1716 : SystemNoOperands<0b000, "pacia1716">;
def PACIB1716 : SystemNoOperands<0b010, "pacib1716">;
- def AUTIA1716 : SystemNoOperands<0b100, "autia1716">;
- def AUTIB1716 : SystemNoOperands<0b110, "autib1716">;
+ let isAuthenticated = 1 in {
+ def AUTIA1716 : SystemNoOperands<0b100, "autia1716">;
+ def AUTIB1716 : SystemNoOperands<0b110, "autib1716">;
+ }
}
let Uses = [LR], Defs = [LR], CRm = 0b0000 in {
diff --git a/llvm/unittests/Target/AArch64/InstSizes.cpp b/llvm/unittests/Target/AArch64/InstSizes.cpp
index 8214d4f41136..74c5d383d8fc 100644
--- a/llvm/unittests/Target/AArch64/InstSizes.cpp
+++ b/llvm/unittests/Target/AArch64/InstSizes.cpp
@@ -78,6 +78,38 @@ void runChecks(
} // anonymous namespace
+TEST(InstSizes, Authenticated) {
+ std::unique_ptr<LLVMTargetMachine> TM = createTargetMachine();
+ ASSERT_TRUE(TM);
+ std::unique_ptr<AArch64InstrInfo> II = createInstrInfo(TM.get());
+
+ auto isAuthInst = [](AArch64InstrInfo &II, MachineFunction &MF) {
+ auto I = MF.begin()->begin();
+ EXPECT_EQ(4u, II.getInstSizeInBytes(*I));
+ EXPECT_TRUE(I->getDesc().isAuthenticated());
+ };
+
+ runChecks(TM.get(), II.get(), "",
+ " \n"
+ " BLRAA $x10, $x9\n",
+ isAuthInst);
+
+ runChecks(TM.get(), II.get(), "",
+ " \n"
+ " RETAB implicit $lr, implicit $sp, implicit killed $x0\n",
+ isAuthInst);
+
+ runChecks(TM.get(), II.get(), "",
+ " \n"
+ " frame-destroy AUTIASP implicit-def $lr, implicit killed $lr, implicit $sp\n",
+ isAuthInst);
+
+ runChecks(TM.get(), II.get(), "",
+ " \n"
+ " frame-destroy AUTIBSP implicit-def $lr, implicit killed $lr, implicit $sp\n",
+ isAuthInst);
+}
+
TEST(InstSizes, STACKMAP) {
std::unique_ptr<LLVMTargetMachine> TM = createTargetMachine();
ASSERT_TRUE(TM);
diff --git a/llvm/utils/TableGen/CodeGenInstruction.cpp b/llvm/utils/TableGen/CodeGenInstruction.cpp
index 095b2653e25c..6bb4dbb511b6 100644
--- a/llvm/utils/TableGen/CodeGenInstruction.cpp
+++ b/llvm/utils/TableGen/CodeGenInstruction.cpp
@@ -396,6 +396,7 @@ CodeGenInstruction::CodeGenInstruction(Record *R)
hasNoSchedulingInfo = R->getValueAsBit("hasNoSchedulingInfo");
FastISelShouldIgnore = R->getValueAsBit("FastISelShouldIgnore");
variadicOpsAreDefs = R->getValueAsBit("variadicOpsAreDefs");
+ isAuthenticated = R->getValueAsBit("isAuthenticated");
bool Unset;
mayLoad = R->getValueAsBitOrUnset("mayLoad", Unset);
diff --git a/llvm/utils/TableGen/CodeGenInstruction.h b/llvm/utils/TableGen/CodeGenInstruction.h
index 573822f56358..1f08ce481a89 100644
--- a/llvm/utils/TableGen/CodeGenInstruction.h
+++ b/llvm/utils/TableGen/CodeGenInstruction.h
@@ -278,6 +278,7 @@ template <typename T> class ArrayRef;
bool hasChain : 1;
bool hasChain_Inferred : 1;
bool variadicOpsAreDefs : 1;
+ bool isAuthenticated : 1;
std::string DeprecatedReason;
bool HasComplexDeprecationPredicate;
diff --git a/llvm/utils/TableGen/InstrDocsEmitter.cpp b/llvm/utils/TableGen/InstrDocsEmitter.cpp
index 45fa936b9574..07efa1885409 100644
--- a/llvm/utils/TableGen/InstrDocsEmitter.cpp
+++ b/llvm/utils/TableGen/InstrDocsEmitter.cpp
@@ -138,6 +138,7 @@ void EmitInstrDocs(RecordKeeper &RK, raw_ostream &OS) {
FLAG(isConvergent)
FLAG(hasNoSchedulingInfo)
FLAG(variadicOpsAreDefs)
+ FLAG(isAuthenticated)
if (!FlagStrings.empty()) {
OS << "Flags: ";
bool IsFirst = true;
diff --git a/llvm/utils/TableGen/InstrInfoEmitter.cpp b/llvm/utils/TableGen/InstrInfoEmitter.cpp
index 3983252b0e04..6ab58bd26a2c 100644
--- a/llvm/utils/TableGen/InstrInfoEmitter.cpp
+++ b/llvm/utils/TableGen/InstrInfoEmitter.cpp
@@ -708,6 +708,7 @@ void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
if (Inst.isInsertSubreg) OS << "|(1ULL<<MCID::InsertSubreg)";
if (Inst.isConvergent) OS << "|(1ULL<<MCID::Convergent)";
if (Inst.variadicOpsAreDefs) OS << "|(1ULL<<MCID::VariadicOpsAreDefs)";
+ if (Inst.isAuthenticated) OS << "|(1ULL<<MCID::Authenticated)";
// Emit all of the target-specific flags...
BitsInit *TSF = Inst.TheDef->getValueAsBitsInit("TSFlags");
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