[PATCH] D72466: [FPEnv][RFC] Invert sense of MIFlag::FPExcept flag

[Pengfei Wang via Phabricator via llvm-commits]

pengfei added inline comments.


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Comment at: llvm/test/CodeGen/X86/fp-intrinsics-flags.ll:9
 ; CHECK: MOVSDmr %stack.0, 1, $noreg, 0, $noreg, killed [[CVTSI2SDrr]] :: (store 8 into %stack.0, align 4)
-; CHECK: [[LD_Fp64m80_:%[0-9]+]]:rfp80 = LD_Fp64m80 %stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 8 from %stack.0, align 4)
+; CHECK: [[LD_Fp64m80_:%[0-9]+]]:rfp80 = nofpexcept LD_Fp64m80 %stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load 8 from %stack.0, align 4)
 ; CHECK: RET 0, killed [[LD_Fp64m80_]]
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pengfei wrote:
> craig.topper wrote:
> > I don't know how to fix this. This is a pattern match from a any extending load instruction. There's no flag to copy from. Unfortunately, X87 generates an exception if you load a NAN from a float or double memory location. But I don't know how to represent that in SelectionDAG or IR.
> SSE instructions don't generate exceptions when only loading from memory to register. Maybe other targets too. And current strict FP semantics don't define a strict load. Can we add masking the `#I` before FLD and FPCW recovery operations into the pattern?
Oh, we also add those instructions in non-strict scenarios. So it's not practicable.


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  https://reviews.llvm.org/D72466/new/

https://reviews.llvm.org/D72466