[PATCH] D72356: [TargetLowering][X86] TeachSimplifyDemanedBits to handle cases where only the sign bit is demanded from a SETCC and can be passed through

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added a comment.

Are you OK with the increase in register pressure? I think this is mainly due to SSE41 BLENDVPS being hard coded to using xmm0 for the selection mask.


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  https://reviews.llvm.org/D72356/new/

https://reviews.llvm.org/D72356