[llvm] 3811417 - [X86] Custom type legalize v4i64->v4f32 uint_to_fp on sse4.1 targets in 64-bit mode
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Wed Jan 8 10:06:49 PST 2020
Author: Craig Topper
Date: 2020-01-08T10:06:01-08:00
New Revision: 3811417f39a7d0a370fac2923060f5ef8dacd8d7
URL: https://github.com/llvm/llvm-project/commit/3811417f39a7d0a370fac2923060f5ef8dacd8d7
DIFF: https://github.com/llvm/llvm-project/commit/3811417f39a7d0a370fac2923060f5ef8dacd8d7.diff
LOG: [X86] Custom type legalize v4i64->v4f32 uint_to_fp on sse4.1 targets in 64-bit mode
For v4i64->v4f32 uint_to_fp on pre-avx targets where v4i64 isn't legal we create to v2i64->v2f32 uint_to_fp that need to be shuffled together. Our codegen for v2i64->v2f32 involves detecting if the number is larger than (2^31 - 1), if so we do a special divison by 2 so we can do a signed conversion which we need to scalarize, then do a multiply by 2 at the end if we divided earlier.
When v4i64 isn't legal we need to split the checking for a larger number and dividing by 2 into two v2i64 vectors. The scalar part can extract the 4 i64 values from those 4 splits. But we can reassemble the 4 scalar f32 results directly into a single v432 vector. Then we just need to combine the fixup indications from the 2 halves and we can do the final multiply by 2 fixup on all 4 values if needed at once using a single v4f32 blend and v4f32 fadd.
Differential Revision: https://reviews.llvm.org/D72368
Added:
Modified:
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/test/CodeGen/X86/vec_int_to_fp.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index c2d76b1be8ac..5cff861221a9 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -1116,6 +1116,17 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
// i8 vectors are custom because the source register and source
// source memory operand types are not the same width.
setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
+
+ if (Subtarget.is64Bit() && !Subtarget.hasAVX512()) {
+ // We need to scalarize v4i64->v432 uint_to_fp using cvtsi2ss, but we can
+ // do the pre and post work in the vector domain.
+ setOperationAction(ISD::UINT_TO_FP, MVT::v4i64, Custom);
+ setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v4i64, Custom);
+ // We need to mark SINT_TO_FP as Custom even though we want to expand it
+ // so that DAG combine doesn't try to turn it into uint_to_fp.
+ setOperationAction(ISD::SINT_TO_FP, MVT::v4i64, Custom);
+ setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v4i64, Custom);
+ }
}
if (!Subtarget.useSoftFloat() && Subtarget.hasXOP()) {
@@ -1176,15 +1187,6 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v8i32, Legal);
- if (Subtarget.is64Bit() && !Subtarget.hasAVX512()) {
- // We need to mark SINT_TO_FP as Custom even though we want to expand it
- // so that DAG combine doesn't try to turn it into uint_to_fp.
- setOperationAction(ISD::SINT_TO_FP, MVT::v4i64, Custom);
- setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v4i64, Custom);
- setOperationAction(ISD::UINT_TO_FP, MVT::v4i64, Custom);
- setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v4i64, Custom);
- }
-
setOperationAction(ISD::STRICT_FP_ROUND, MVT::v4f32, Legal);
setOperationAction(ISD::STRICT_FADD, MVT::v8f32, Legal);
setOperationAction(ISD::STRICT_FADD, MVT::v4f64, Legal);
diff --git a/llvm/test/CodeGen/X86/vec_int_to_fp.ll b/llvm/test/CodeGen/X86/vec_int_to_fp.ll
index 989804a05f79..daa8bd97d3de 100644
--- a/llvm/test/CodeGen/X86/vec_int_to_fp.ll
+++ b/llvm/test/CodeGen/X86/vec_int_to_fp.ll
@@ -2138,7 +2138,7 @@ define <4 x float> @uitofp_4i64_to_4f32_undef(<2 x i64> %a) {
; SSE41-NEXT: addps %xmm1, %xmm2
; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,3,2,3]
; SSE41-NEXT: blendvps %xmm0, %xmm2, %xmm1
-; SSE41-NEXT: movq {{.*#+}} xmm0 = xmm1[0],zero
+; SSE41-NEXT: movaps %xmm1, %xmm0
; SSE41-NEXT: retq
;
; AVX1-LABEL: uitofp_4i64_to_4f32_undef:
@@ -2519,48 +2519,43 @@ define <4 x float> @uitofp_4i64_to_4f32(<4 x i64> %a) {
;
; SSE41-LABEL: uitofp_4i64_to_4f32:
; SSE41: # %bb.0:
-; SSE41-NEXT: movdqa %xmm0, %xmm2
-; SSE41-NEXT: pxor %xmm3, %xmm3
-; SSE41-NEXT: pxor %xmm0, %xmm0
-; SSE41-NEXT: pcmpgtd %xmm1, %xmm0
-; SSE41-NEXT: movdqa {{.*#+}} xmm5 = [1,1]
-; SSE41-NEXT: movdqa %xmm1, %xmm4
-; SSE41-NEXT: pand %xmm5, %xmm4
-; SSE41-NEXT: movdqa %xmm1, %xmm6
-; SSE41-NEXT: psrlq $1, %xmm6
-; SSE41-NEXT: por %xmm4, %xmm6
-; SSE41-NEXT: blendvpd %xmm0, %xmm6, %xmm1
-; SSE41-NEXT: pextrq $1, %xmm1, %rax
-; SSE41-NEXT: xorps %xmm6, %xmm6
-; SSE41-NEXT: cvtsi2ss %rax, %xmm6
-; SSE41-NEXT: movq %xmm1, %rax
-; SSE41-NEXT: xorps %xmm4, %xmm4
-; SSE41-NEXT: cvtsi2ss %rax, %xmm4
-; SSE41-NEXT: insertps {{.*#+}} xmm4 = xmm4[0],xmm6[0],zero,zero
-; SSE41-NEXT: movaps %xmm4, %xmm1
-; SSE41-NEXT: addps %xmm4, %xmm1
-; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,3,2,3]
-; SSE41-NEXT: blendvps %xmm0, %xmm1, %xmm4
-; SSE41-NEXT: pcmpgtd %xmm2, %xmm3
-; SSE41-NEXT: pand %xmm2, %xmm5
-; SSE41-NEXT: movdqa %xmm2, %xmm1
-; SSE41-NEXT: psrlq $1, %xmm1
-; SSE41-NEXT: por %xmm5, %xmm1
-; SSE41-NEXT: movdqa %xmm3, %xmm0
-; SSE41-NEXT: blendvpd %xmm0, %xmm1, %xmm2
-; SSE41-NEXT: pextrq $1, %xmm2, %rax
+; SSE41-NEXT: movdqa %xmm1, %xmm2
+; SSE41-NEXT: movdqa %xmm0, %xmm1
+; SSE41-NEXT: movdqa {{.*#+}} xmm4 = [1,1]
+; SSE41-NEXT: pand %xmm4, %xmm0
+; SSE41-NEXT: movdqa %xmm1, %xmm3
+; SSE41-NEXT: psrlq $1, %xmm3
+; SSE41-NEXT: por %xmm0, %xmm3
+; SSE41-NEXT: movdqa %xmm1, %xmm5
+; SSE41-NEXT: movdqa %xmm1, %xmm0
+; SSE41-NEXT: blendvpd %xmm0, %xmm3, %xmm5
+; SSE41-NEXT: pextrq $1, %xmm5, %rax
; SSE41-NEXT: xorps %xmm0, %xmm0
; SSE41-NEXT: cvtsi2ss %rax, %xmm0
+; SSE41-NEXT: movq %xmm5, %rax
+; SSE41-NEXT: xorps %xmm3, %xmm3
+; SSE41-NEXT: cvtsi2ss %rax, %xmm3
+; SSE41-NEXT: insertps {{.*#+}} xmm3 = xmm3[0],xmm0[0],xmm3[2,3]
+; SSE41-NEXT: pand %xmm2, %xmm4
+; SSE41-NEXT: movdqa %xmm2, %xmm5
+; SSE41-NEXT: psrlq $1, %xmm5
+; SSE41-NEXT: por %xmm4, %xmm5
+; SSE41-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,3],xmm2[1,3]
+; SSE41-NEXT: movaps %xmm2, %xmm0
+; SSE41-NEXT: blendvpd %xmm0, %xmm5, %xmm2
; SSE41-NEXT: movq %xmm2, %rax
-; SSE41-NEXT: xorps %xmm1, %xmm1
-; SSE41-NEXT: cvtsi2ss %rax, %xmm1
-; SSE41-NEXT: insertps {{.*#+}} xmm1 = xmm1[0],xmm0[0],zero,zero
-; SSE41-NEXT: movaps %xmm1, %xmm2
-; SSE41-NEXT: addps %xmm1, %xmm2
-; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm3[1,3,2,3]
-; SSE41-NEXT: blendvps %xmm0, %xmm2, %xmm1
-; SSE41-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm4[0]
+; SSE41-NEXT: xorps %xmm0, %xmm0
+; SSE41-NEXT: cvtsi2ss %rax, %xmm0
+; SSE41-NEXT: insertps {{.*#+}} xmm3 = xmm3[0,1],xmm0[0],xmm3[3]
+; SSE41-NEXT: pextrq $1, %xmm2, %rax
+; SSE41-NEXT: xorps %xmm0, %xmm0
+; SSE41-NEXT: cvtsi2ss %rax, %xmm0
+; SSE41-NEXT: insertps {{.*#+}} xmm3 = xmm3[0,1,2],xmm0[0]
+; SSE41-NEXT: movaps %xmm3, %xmm2
+; SSE41-NEXT: addps %xmm3, %xmm2
; SSE41-NEXT: movaps %xmm1, %xmm0
+; SSE41-NEXT: blendvps %xmm0, %xmm2, %xmm3
+; SSE41-NEXT: movaps %xmm3, %xmm0
; SSE41-NEXT: retq
;
; AVX1-LABEL: uitofp_4i64_to_4f32:
@@ -4436,49 +4431,44 @@ define <4 x float> @uitofp_load_4i64_to_4f32(<4 x i64> *%a) {
;
; SSE41-LABEL: uitofp_load_4i64_to_4f32:
; SSE41: # %bb.0:
-; SSE41-NEXT: movdqa (%rdi), %xmm2
-; SSE41-NEXT: movdqa 16(%rdi), %xmm3
-; SSE41-NEXT: pxor %xmm1, %xmm1
-; SSE41-NEXT: pxor %xmm0, %xmm0
-; SSE41-NEXT: pcmpgtd %xmm3, %xmm0
+; SSE41-NEXT: movdqa (%rdi), %xmm1
+; SSE41-NEXT: movdqa 16(%rdi), %xmm2
; SSE41-NEXT: movdqa {{.*#+}} xmm4 = [1,1]
-; SSE41-NEXT: movdqa %xmm3, %xmm5
-; SSE41-NEXT: pand %xmm4, %xmm5
-; SSE41-NEXT: movdqa %xmm3, %xmm6
-; SSE41-NEXT: psrlq $1, %xmm6
-; SSE41-NEXT: por %xmm5, %xmm6
-; SSE41-NEXT: blendvpd %xmm0, %xmm6, %xmm3
-; SSE41-NEXT: pextrq $1, %xmm3, %rax
-; SSE41-NEXT: xorps %xmm5, %xmm5
-; SSE41-NEXT: cvtsi2ss %rax, %xmm5
-; SSE41-NEXT: movq %xmm3, %rax
+; SSE41-NEXT: movdqa %xmm1, %xmm0
+; SSE41-NEXT: pand %xmm4, %xmm0
+; SSE41-NEXT: movdqa %xmm1, %xmm3
+; SSE41-NEXT: psrlq $1, %xmm3
+; SSE41-NEXT: por %xmm0, %xmm3
+; SSE41-NEXT: movdqa %xmm1, %xmm5
+; SSE41-NEXT: movdqa %xmm1, %xmm0
+; SSE41-NEXT: blendvpd %xmm0, %xmm3, %xmm5
+; SSE41-NEXT: pextrq $1, %xmm5, %rax
+; SSE41-NEXT: xorps %xmm0, %xmm0
+; SSE41-NEXT: cvtsi2ss %rax, %xmm0
+; SSE41-NEXT: movq %xmm5, %rax
; SSE41-NEXT: xorps %xmm3, %xmm3
; SSE41-NEXT: cvtsi2ss %rax, %xmm3
-; SSE41-NEXT: insertps {{.*#+}} xmm3 = xmm3[0],xmm5[0],zero,zero
-; SSE41-NEXT: movaps %xmm3, %xmm5
-; SSE41-NEXT: addps %xmm3, %xmm5
-; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,3,2,3]
-; SSE41-NEXT: blendvps %xmm0, %xmm5, %xmm3
-; SSE41-NEXT: pcmpgtd %xmm2, %xmm1
+; SSE41-NEXT: insertps {{.*#+}} xmm3 = xmm3[0],xmm0[0],xmm3[2,3]
; SSE41-NEXT: pand %xmm2, %xmm4
; SSE41-NEXT: movdqa %xmm2, %xmm5
; SSE41-NEXT: psrlq $1, %xmm5
; SSE41-NEXT: por %xmm4, %xmm5
-; SSE41-NEXT: movdqa %xmm1, %xmm0
+; SSE41-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,3],xmm2[1,3]
+; SSE41-NEXT: movaps %xmm2, %xmm0
; SSE41-NEXT: blendvpd %xmm0, %xmm5, %xmm2
+; SSE41-NEXT: movq %xmm2, %rax
+; SSE41-NEXT: xorps %xmm0, %xmm0
+; SSE41-NEXT: cvtsi2ss %rax, %xmm0
+; SSE41-NEXT: insertps {{.*#+}} xmm3 = xmm3[0,1],xmm0[0],xmm3[3]
; SSE41-NEXT: pextrq $1, %xmm2, %rax
; SSE41-NEXT: xorps %xmm0, %xmm0
; SSE41-NEXT: cvtsi2ss %rax, %xmm0
-; SSE41-NEXT: movq %xmm2, %rax
-; SSE41-NEXT: xorps %xmm2, %xmm2
-; SSE41-NEXT: cvtsi2ss %rax, %xmm2
-; SSE41-NEXT: insertps {{.*#+}} xmm2 = xmm2[0],xmm0[0],zero,zero
-; SSE41-NEXT: movaps %xmm2, %xmm4
-; SSE41-NEXT: addps %xmm2, %xmm4
-; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,3,2,3]
-; SSE41-NEXT: blendvps %xmm0, %xmm4, %xmm2
-; SSE41-NEXT: movlhps {{.*#+}} xmm2 = xmm2[0],xmm3[0]
-; SSE41-NEXT: movaps %xmm2, %xmm0
+; SSE41-NEXT: insertps {{.*#+}} xmm3 = xmm3[0,1,2],xmm0[0]
+; SSE41-NEXT: movaps %xmm3, %xmm2
+; SSE41-NEXT: addps %xmm3, %xmm2
+; SSE41-NEXT: movaps %xmm1, %xmm0
+; SSE41-NEXT: blendvps %xmm0, %xmm2, %xmm3
+; SSE41-NEXT: movaps %xmm3, %xmm0
; SSE41-NEXT: retq
;
; AVX1-LABEL: uitofp_load_4i64_to_4f32:
@@ -4862,90 +4852,81 @@ define <8 x float> @uitofp_load_8i64_to_8f32(<8 x i64> *%a) {
;
; SSE41-LABEL: uitofp_load_8i64_to_8f32:
; SSE41: # %bb.0:
-; SSE41-NEXT: movdqa (%rdi), %xmm2
-; SSE41-NEXT: movdqa 16(%rdi), %xmm7
-; SSE41-NEXT: movdqa 32(%rdi), %xmm1
-; SSE41-NEXT: movdqa 48(%rdi), %xmm5
-; SSE41-NEXT: pxor %xmm8, %xmm8
-; SSE41-NEXT: pxor %xmm0, %xmm0
-; SSE41-NEXT: pcmpgtd %xmm7, %xmm0
-; SSE41-NEXT: movdqa {{.*#+}} xmm4 = [1,1]
-; SSE41-NEXT: movdqa %xmm7, %xmm3
-; SSE41-NEXT: pand %xmm4, %xmm3
-; SSE41-NEXT: movdqa %xmm7, %xmm6
-; SSE41-NEXT: psrlq $1, %xmm6
-; SSE41-NEXT: por %xmm3, %xmm6
-; SSE41-NEXT: blendvpd %xmm0, %xmm6, %xmm7
-; SSE41-NEXT: pextrq $1, %xmm7, %rax
-; SSE41-NEXT: xorps %xmm3, %xmm3
-; SSE41-NEXT: cvtsi2ss %rax, %xmm3
-; SSE41-NEXT: movq %xmm7, %rax
-; SSE41-NEXT: xorps %xmm6, %xmm6
-; SSE41-NEXT: cvtsi2ss %rax, %xmm6
-; SSE41-NEXT: insertps {{.*#+}} xmm6 = xmm6[0],xmm3[0],zero,zero
-; SSE41-NEXT: movaps %xmm6, %xmm3
-; SSE41-NEXT: addps %xmm6, %xmm3
-; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,3,2,3]
-; SSE41-NEXT: blendvps %xmm0, %xmm3, %xmm6
-; SSE41-NEXT: pxor %xmm0, %xmm0
-; SSE41-NEXT: pcmpgtd %xmm2, %xmm0
-; SSE41-NEXT: movdqa %xmm2, %xmm3
-; SSE41-NEXT: pand %xmm4, %xmm3
-; SSE41-NEXT: movdqa %xmm2, %xmm7
-; SSE41-NEXT: psrlq $1, %xmm7
-; SSE41-NEXT: por %xmm3, %xmm7
-; SSE41-NEXT: blendvpd %xmm0, %xmm7, %xmm2
-; SSE41-NEXT: pextrq $1, %xmm2, %rax
-; SSE41-NEXT: xorps %xmm3, %xmm3
-; SSE41-NEXT: cvtsi2ss %rax, %xmm3
-; SSE41-NEXT: movq %xmm2, %rax
-; SSE41-NEXT: xorps %xmm2, %xmm2
-; SSE41-NEXT: cvtsi2ss %rax, %xmm2
-; SSE41-NEXT: insertps {{.*#+}} xmm2 = xmm2[0],xmm3[0],zero,zero
-; SSE41-NEXT: movaps %xmm2, %xmm3
-; SSE41-NEXT: addps %xmm2, %xmm3
-; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,3,2,3]
-; SSE41-NEXT: blendvps %xmm0, %xmm3, %xmm2
-; SSE41-NEXT: movlhps {{.*#+}} xmm2 = xmm2[0],xmm6[0]
-; SSE41-NEXT: pxor %xmm0, %xmm0
-; SSE41-NEXT: pcmpgtd %xmm5, %xmm0
-; SSE41-NEXT: movdqa %xmm5, %xmm3
-; SSE41-NEXT: pand %xmm4, %xmm3
-; SSE41-NEXT: movdqa %xmm5, %xmm6
-; SSE41-NEXT: psrlq $1, %xmm6
-; SSE41-NEXT: por %xmm3, %xmm6
-; SSE41-NEXT: blendvpd %xmm0, %xmm6, %xmm5
-; SSE41-NEXT: pextrq $1, %xmm5, %rax
+; SSE41-NEXT: movdqa (%rdi), %xmm4
+; SSE41-NEXT: movdqa 16(%rdi), %xmm5
+; SSE41-NEXT: movdqa 32(%rdi), %xmm6
+; SSE41-NEXT: movdqa 48(%rdi), %xmm2
+; SSE41-NEXT: movdqa {{.*#+}} xmm7 = [1,1]
+; SSE41-NEXT: movdqa %xmm4, %xmm0
+; SSE41-NEXT: pand %xmm7, %xmm0
+; SSE41-NEXT: movdqa %xmm4, %xmm1
+; SSE41-NEXT: psrlq $1, %xmm1
+; SSE41-NEXT: por %xmm0, %xmm1
+; SSE41-NEXT: movdqa %xmm4, %xmm3
+; SSE41-NEXT: movdqa %xmm4, %xmm0
+; SSE41-NEXT: blendvpd %xmm0, %xmm1, %xmm3
+; SSE41-NEXT: pextrq $1, %xmm3, %rax
+; SSE41-NEXT: xorps %xmm0, %xmm0
+; SSE41-NEXT: cvtsi2ss %rax, %xmm0
+; SSE41-NEXT: movq %xmm3, %rax
; SSE41-NEXT: xorps %xmm3, %xmm3
; SSE41-NEXT: cvtsi2ss %rax, %xmm3
+; SSE41-NEXT: insertps {{.*#+}} xmm3 = xmm3[0],xmm0[0],xmm3[2,3]
+; SSE41-NEXT: movdqa %xmm5, %xmm0
+; SSE41-NEXT: pand %xmm7, %xmm0
+; SSE41-NEXT: movdqa %xmm5, %xmm1
+; SSE41-NEXT: psrlq $1, %xmm1
+; SSE41-NEXT: por %xmm0, %xmm1
+; SSE41-NEXT: shufps {{.*#+}} xmm4 = xmm4[1,3],xmm5[1,3]
+; SSE41-NEXT: movaps %xmm5, %xmm0
+; SSE41-NEXT: blendvpd %xmm0, %xmm1, %xmm5
; SSE41-NEXT: movq %xmm5, %rax
-; SSE41-NEXT: xorps %xmm5, %xmm5
-; SSE41-NEXT: cvtsi2ss %rax, %xmm5
-; SSE41-NEXT: insertps {{.*#+}} xmm5 = xmm5[0],xmm3[0],zero,zero
-; SSE41-NEXT: movaps %xmm5, %xmm3
-; SSE41-NEXT: addps %xmm5, %xmm3
-; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,3,2,3]
-; SSE41-NEXT: blendvps %xmm0, %xmm3, %xmm5
-; SSE41-NEXT: pcmpgtd %xmm1, %xmm8
-; SSE41-NEXT: pand %xmm1, %xmm4
-; SSE41-NEXT: movdqa %xmm1, %xmm3
-; SSE41-NEXT: psrlq $1, %xmm3
-; SSE41-NEXT: por %xmm4, %xmm3
-; SSE41-NEXT: movdqa %xmm8, %xmm0
-; SSE41-NEXT: blendvpd %xmm0, %xmm3, %xmm1
-; SSE41-NEXT: pextrq $1, %xmm1, %rax
; SSE41-NEXT: xorps %xmm0, %xmm0
; SSE41-NEXT: cvtsi2ss %rax, %xmm0
-; SSE41-NEXT: movq %xmm1, %rax
+; SSE41-NEXT: insertps {{.*#+}} xmm3 = xmm3[0,1],xmm0[0],xmm3[3]
+; SSE41-NEXT: pextrq $1, %xmm5, %rax
+; SSE41-NEXT: xorps %xmm0, %xmm0
+; SSE41-NEXT: cvtsi2ss %rax, %xmm0
+; SSE41-NEXT: insertps {{.*#+}} xmm3 = xmm3[0,1,2],xmm0[0]
+; SSE41-NEXT: movaps %xmm3, %xmm1
+; SSE41-NEXT: addps %xmm3, %xmm1
+; SSE41-NEXT: movaps %xmm4, %xmm0
+; SSE41-NEXT: blendvps %xmm0, %xmm1, %xmm3
+; SSE41-NEXT: movdqa %xmm6, %xmm0
+; SSE41-NEXT: pand %xmm7, %xmm0
+; SSE41-NEXT: movdqa %xmm6, %xmm1
+; SSE41-NEXT: psrlq $1, %xmm1
+; SSE41-NEXT: por %xmm0, %xmm1
+; SSE41-NEXT: movdqa %xmm6, %xmm4
+; SSE41-NEXT: movdqa %xmm6, %xmm0
+; SSE41-NEXT: blendvpd %xmm0, %xmm1, %xmm4
+; SSE41-NEXT: pextrq $1, %xmm4, %rax
+; SSE41-NEXT: xorps %xmm0, %xmm0
+; SSE41-NEXT: cvtsi2ss %rax, %xmm0
+; SSE41-NEXT: movq %xmm4, %rax
; SSE41-NEXT: xorps %xmm1, %xmm1
; SSE41-NEXT: cvtsi2ss %rax, %xmm1
-; SSE41-NEXT: insertps {{.*#+}} xmm1 = xmm1[0],xmm0[0],zero,zero
-; SSE41-NEXT: movaps %xmm1, %xmm3
-; SSE41-NEXT: addps %xmm1, %xmm3
-; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm8[1,3,2,3]
-; SSE41-NEXT: blendvps %xmm0, %xmm3, %xmm1
-; SSE41-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm5[0]
+; SSE41-NEXT: insertps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[2,3]
+; SSE41-NEXT: pand %xmm2, %xmm7
+; SSE41-NEXT: movdqa %xmm2, %xmm4
+; SSE41-NEXT: psrlq $1, %xmm4
+; SSE41-NEXT: por %xmm7, %xmm4
+; SSE41-NEXT: shufps {{.*#+}} xmm6 = xmm6[1,3],xmm2[1,3]
; SSE41-NEXT: movaps %xmm2, %xmm0
+; SSE41-NEXT: blendvpd %xmm0, %xmm4, %xmm2
+; SSE41-NEXT: movq %xmm2, %rax
+; SSE41-NEXT: xorps %xmm0, %xmm0
+; SSE41-NEXT: cvtsi2ss %rax, %xmm0
+; SSE41-NEXT: insertps {{.*#+}} xmm1 = xmm1[0,1],xmm0[0],xmm1[3]
+; SSE41-NEXT: pextrq $1, %xmm2, %rax
+; SSE41-NEXT: xorps %xmm0, %xmm0
+; SSE41-NEXT: cvtsi2ss %rax, %xmm0
+; SSE41-NEXT: insertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm0[0]
+; SSE41-NEXT: movaps %xmm1, %xmm2
+; SSE41-NEXT: addps %xmm1, %xmm2
+; SSE41-NEXT: movaps %xmm6, %xmm0
+; SSE41-NEXT: blendvps %xmm0, %xmm2, %xmm1
+; SSE41-NEXT: movaps %xmm3, %xmm0
; SSE41-NEXT: retq
;
; AVX1-LABEL: uitofp_load_8i64_to_8f32:
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