[llvm] ee81180 - [ARM][MVE] Renamed VPT Block tests and files to something more informative. NFC
Sjoerd Meijer via llvm-commits
llvm-commits at lists.llvm.org
Tue Jan 7 08:17:11 PST 2020
Author: Sjoerd Meijer
Date: 2020-01-07T16:16:54Z
New Revision: ee811808a9a0e16a1b48d70cbe5d95525733d347
URL: https://github.com/llvm/llvm-project/commit/ee811808a9a0e16a1b48d70cbe5d95525733d347
DIFF: https://github.com/llvm/llvm-project/commit/ee811808a9a0e16a1b48d70cbe5d95525733d347.diff
LOG: [ARM][MVE] Renamed VPT Block tests and files to something more informative. NFC
Added:
llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-2-preds.mir
llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-ctrl-flow.mir
llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-non-consecutive-ins.mir
llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks.mir
llvm/test/CodeGen/Thumb2/mve-vpt-3-blocks-kill-vpr.mir
llvm/test/CodeGen/Thumb2/mve-vpt-block-1-ins.mir
llvm/test/CodeGen/Thumb2/mve-vpt-block-2-ins.mir
llvm/test/CodeGen/Thumb2/mve-vpt-block-4-ins.mir
Modified:
Removed:
llvm/test/CodeGen/Thumb2/mve-vpt-block.mir
llvm/test/CodeGen/Thumb2/mve-vpt-block2.mir
llvm/test/CodeGen/Thumb2/mve-vpt-block3.mir
llvm/test/CodeGen/Thumb2/mve-vpt-block4.mir
llvm/test/CodeGen/Thumb2/mve-vpt-block5.mir
llvm/test/CodeGen/Thumb2/mve-vpt-block6.mir
llvm/test/CodeGen/Thumb2/mve-vpt-block7.mir
llvm/test/CodeGen/Thumb2/mve-vpt-block8.mir
################################################################################
diff --git a/llvm/test/CodeGen/Thumb2/mve-vpt-block6.mir b/llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-2-preds.mir
similarity index 93%
rename from llvm/test/CodeGen/Thumb2/mve-vpt-block6.mir
rename to llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-2-preds.mir
index 7ec17597be0f..4b520910a567 100644
--- a/llvm/test/CodeGen/Thumb2/mve-vpt-block6.mir
+++ b/llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-2-preds.mir
@@ -5,7 +5,7 @@
target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
target triple = "thumbv8.1m.main-arm-none-eabi"
- define hidden arm_aapcs_vfpcc <4 x float> @test_vminnmq_m_f32_v2(<4 x float> %inactive1, <4 x float> %a, <4 x float> %b, i16 zeroext %p1, i16 zeroext %p2) local_unnamed_addr #0 {
+ define hidden arm_aapcs_vfpcc <4 x float> @vpt_2_blocks_2_preds(<4 x float> %inactive1, <4 x float> %a, <4 x float> %b, i16 zeroext %p1, i16 zeroext %p2) local_unnamed_addr #0 {
entry:
%conv.i = zext i16 %p1 to i32
%0 = tail call nnan ninf nsz <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float> %inactive1, <4 x float> %a, <4 x float> %b, i32 %conv.i) #2
@@ -22,7 +22,7 @@
...
---
-name: test_vminnmq_m_f32_v2
+name: vpt_2_blocks_2_preds
alignment: 4
exposesReturnsTwice: false
legalized: false
@@ -64,7 +64,7 @@ body: |
bb.0.entry:
liveins: $q0, $q1, $q2, $r0, $r1
- ; CHECK-LABEL: name: test_vminnmq_m_f32_v2
+ ; CHECK-LABEL: name: vpt_2_blocks_2_preds
; CHECK: liveins: $q0, $q1, $q2, $r0, $r1
; CHECK: $vpr = VMSR_P0 killed $r0, 14, $noreg
; CHECK: $q3 = MVE_VORR $q0, $q0, 0, $noreg, undef $q3
diff --git a/llvm/test/CodeGen/Thumb2/mve-vpt-block7.mir b/llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-ctrl-flow.mir
similarity index 95%
rename from llvm/test/CodeGen/Thumb2/mve-vpt-block7.mir
rename to llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-ctrl-flow.mir
index 1c35c758e567..9e429704a019 100644
--- a/llvm/test/CodeGen/Thumb2/mve-vpt-block7.mir
+++ b/llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-ctrl-flow.mir
@@ -5,7 +5,7 @@
target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
target triple = "thumbv8.1m.main-arm-none-eabi"
- define hidden arm_aapcs_vfpcc <4 x float> @test_vminnmq_m_f32_v2(<4 x float> %inactive1, <4 x float> %a, <4 x float> %b, i16 zeroext %p) local_unnamed_addr #0 {
+ define hidden arm_aapcs_vfpcc <4 x float> @vpt_2_blocks_ctrl_flow(<4 x float> %inactive1, <4 x float> %a, <4 x float> %b, i16 zeroext %p) local_unnamed_addr #0 {
entry:
%conv.i = zext i16 %p to i32
%0 = tail call nnan ninf nsz <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float> %inactive1, <4 x float> %a, <4 x float> %b, i32 %conv.i) #2
@@ -25,7 +25,7 @@
...
---
-name: test_vminnmq_m_f32_v2
+name: vpt_2_blocks_ctrl_flow
alignment: 4
exposesReturnsTwice: false
legalized: false
@@ -63,7 +63,7 @@ fixedStack: []
stack: []
constants: []
body: |
- ; CHECK-LABEL: name: test_vminnmq_m_f32_v2
+ ; CHECK-LABEL: name: vpt_2_blocks_ctrl_flow
; CHECK: bb.0.entry:
; CHECK: successors: %bb.1(0x80000000)
; CHECK: liveins: $q0, $q1, $q2, $r0
diff --git a/llvm/test/CodeGen/Thumb2/mve-vpt-block5.mir b/llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-non-consecutive-ins.mir
similarity index 94%
rename from llvm/test/CodeGen/Thumb2/mve-vpt-block5.mir
rename to llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-non-consecutive-ins.mir
index d02c25796076..9f85c219ec37 100644
--- a/llvm/test/CodeGen/Thumb2/mve-vpt-block5.mir
+++ b/llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-non-consecutive-ins.mir
@@ -5,7 +5,7 @@
target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
target triple = "thumbv8.1m.main-arm-none-eabi"
- define hidden arm_aapcs_vfpcc <4 x float> @test_vminnmq_m_f32_v2(<4 x float> %inactive1, <4 x float> %a, <4 x float> %b, i16 zeroext %p) local_unnamed_addr #0 {
+ define hidden arm_aapcs_vfpcc <4 x float> @vpt_2_blocks_non_consecutive_ins(<4 x float> %inactive1, <4 x float> %a, <4 x float> %b, i16 zeroext %p) local_unnamed_addr #0 {
entry:
%conv.i = zext i16 %p to i32
%0 = tail call nnan ninf nsz <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float> %inactive1, <4 x float> %a, <4 x float> %b, i32 %conv.i) #2
@@ -23,7 +23,7 @@
...
---
-name: test_vminnmq_m_f32_v2
+name: vpt_2_blocks_non_consecutive_ins
alignment: 4
exposesReturnsTwice: false
legalized: false
@@ -64,7 +64,7 @@ body: |
bb.0.entry:
liveins: $q0, $q1, $q2, $r0
- ; CHECK-LABEL: name: test_vminnmq_m_f32_v2
+ ; CHECK-LABEL: name: vpt_2_blocks_non_consecutive_ins
; CHECK: liveins: $q0, $q1, $q2, $r0
; CHECK: $vpr = VMSR_P0 killed $r0, 14, $noreg
; CHECK: $q3 = MVE_VORR $q0, $q0, 0, $noreg, undef $q3
@@ -80,11 +80,14 @@ body: |
; CHECK: renamable $q0 = nnan ninf nsz MVE_VMINNMf32 internal killed renamable $q3, killed renamable $q2, 1, killed renamable $vpr, killed renamable $q0
; CHECK: }
; CHECK: tBX_RET 14, $noreg, implicit $q0
+
$vpr = VMSR_P0 killed $r0, 14, $noreg
$q3 = MVE_VORR $q0, $q0, 0, $noreg, undef $q3
renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr, killed renamable $q3
renamable $q1 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q3, renamable $q3, 1, renamable $vpr, undef renamable $q1
+
$q3 = MVE_VORR $q0, $q0, 0, $noreg, undef $q3
+
renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr, killed renamable $q3
renamable $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q3, killed renamable $q2, 1, killed renamable $vpr, killed renamable $q0
tBX_RET 14, $noreg, implicit $q0
diff --git a/llvm/test/CodeGen/Thumb2/mve-vpt-block4.mir b/llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks.mir
similarity index 94%
rename from llvm/test/CodeGen/Thumb2/mve-vpt-block4.mir
rename to llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks.mir
index 36d86ec7ee0d..b8f61e4a992d 100644
--- a/llvm/test/CodeGen/Thumb2/mve-vpt-block4.mir
+++ b/llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks.mir
@@ -5,7 +5,7 @@
target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
target triple = "thumbv8.1m.main-arm-none-eabi"
- define hidden arm_aapcs_vfpcc <4 x float> @test_vminnmq_m_f32_v2(<4 x float> %inactive1, <4 x float> %inactive2, <4 x float> %a, <4 x float> %b, i16 zeroext %p) local_unnamed_addr #0 {
+ define hidden arm_aapcs_vfpcc <4 x float> @vpt_2_blocks(<4 x float> %inactive1, <4 x float> %inactive2, <4 x float> %a, <4 x float> %b, i16 zeroext %p) local_unnamed_addr #0 {
entry:
%conv.i = zext i16 %p to i32
%0 = tail call nnan ninf nsz <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float> undef, <4 x float> %a, <4 x float> %b, i32 %conv.i) #2
@@ -17,7 +17,6 @@
}
declare <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float>, <4 x float>, <4 x float>, i32) #1
- declare void @llvm.stackprotector(i8*, i8**) #2
attributes #0 = { nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "denormal-fp-math"="preserve-sign" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="128" "frame-pointer"="none" "no-infs-fp-math"="true" "no-jump-tables"="false" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+armv8.1-m.main,+hwdiv,+mve.fp,+ras,+thumb-mode" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #1 = { nounwind readnone }
@@ -25,7 +24,7 @@
...
---
-name: test_vminnmq_m_f32_v2
+name: vpt_2_blocks
alignment: 4
exposesReturnsTwice: false
legalized: false
@@ -67,7 +66,7 @@ body: |
bb.0.entry:
liveins: $q0, $q1, $q2, $q3, $r0
- ; CHECK-LABEL: name: test_vminnmq_m_f32_v2
+ ; CHECK-LABEL: name: vpt_2_blocks
; CHECK: liveins: $q0, $q1, $q2, $q3, $r0
; CHECK: $vpr = VMSR_P0 killed $r0, 14, $noreg
; CHECK: BUNDLE implicit-def dead $q2, implicit-def $d4, implicit-def $s8, implicit-def $s9, implicit-def $d5, implicit-def $s10, implicit-def $s11, implicit-def $q0, implicit-def $d0, implicit-def $s0, implicit-def $s1, implicit-def $d1, implicit-def $s2, implicit-def $s3, implicit $vpr, implicit killed $q2, implicit $q3, implicit killed $q0 {
diff --git a/llvm/test/CodeGen/Thumb2/mve-vpt-block8.mir b/llvm/test/CodeGen/Thumb2/mve-vpt-3-blocks-kill-vpr.mir
similarity index 96%
rename from llvm/test/CodeGen/Thumb2/mve-vpt-block8.mir
rename to llvm/test/CodeGen/Thumb2/mve-vpt-3-blocks-kill-vpr.mir
index 45ff8bfba1c3..268b3a84b6aa 100644
--- a/llvm/test/CodeGen/Thumb2/mve-vpt-block8.mir
+++ b/llvm/test/CodeGen/Thumb2/mve-vpt-3-blocks-kill-vpr.mir
@@ -5,7 +5,7 @@
target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
target triple = "thumbv8.1m.main-arm-none-eabi"
- define hidden arm_aapcs_vfpcc <4 x float> @test_vminnmq_m_f32_v2(<4 x float> %inactive1, <4 x float> %a, <4 x float> %b, i16 zeroext %p) local_unnamed_addr #0 {
+ define hidden arm_aapcs_vfpcc <4 x float> @vpt_3_blocks_kill_vpr(<4 x float> %inactive1, <4 x float> %a, <4 x float> %b, i16 zeroext %p) local_unnamed_addr #0 {
entry:
%conv.i = zext i16 %p to i32
%0 = tail call nnan ninf nsz <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float> %inactive1, <4 x float> %a, <4 x float> %b, i32 %conv.i) #2
@@ -23,7 +23,7 @@
...
---
-name: test_vminnmq_m_f32_v2
+name: vpt_3_blocks_kill_vpr
alignment: 4
exposesReturnsTwice: false
legalized: false
@@ -64,7 +64,7 @@ body: |
bb.0.entry:
liveins: $q0, $q1, $q2, $r0
- ; CHECK-LABEL: name: test_vminnmq_m_f32_v2
+ ; CHECK-LABEL: name: vpt_3_blocks_kill_vpr
; CHECK: liveins: $q0, $q1, $q2, $r0
; CHECK: $vpr = VMSR_P0 killed $r0, 14, $noreg
; CHECK: $q3 = MVE_VORR $q0, $q0, 0, $noreg, undef $q3
diff --git a/llvm/test/CodeGen/Thumb2/mve-vpt-block.mir b/llvm/test/CodeGen/Thumb2/mve-vpt-block-1-ins.mir
similarity index 92%
rename from llvm/test/CodeGen/Thumb2/mve-vpt-block.mir
rename to llvm/test/CodeGen/Thumb2/mve-vpt-block-1-ins.mir
index eba97a683e5e..3b146ebb1e56 100644
--- a/llvm/test/CodeGen/Thumb2/mve-vpt-block.mir
+++ b/llvm/test/CodeGen/Thumb2/mve-vpt-block-1-ins.mir
@@ -5,7 +5,7 @@
target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
target triple = "thumbv8.1m.main-arm-none-eabi"
- define hidden arm_aapcs_vfpcc <4 x float> @test_vminnmq_m_f32_v2(<4 x float> %inactive, <4 x float> %a, <4 x float> %b, i16 zeroext %p) local_unnamed_addr #0 {
+ define hidden arm_aapcs_vfpcc <4 x float> @vpt_block_1_ins(<4 x float> %inactive, <4 x float> %a, <4 x float> %b, i16 zeroext %p) local_unnamed_addr #0 {
entry:
%conv.i = zext i16 %p to i32
%0 = tail call nnan ninf nsz <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float> %inactive, <4 x float> %a, <4 x float> %b, i32 %conv.i) #2
@@ -21,7 +21,7 @@
...
---
-name: test_vminnmq_m_f32_v2
+name: vpt_block_1_ins
alignment: 4
exposesReturnsTwice: false
legalized: false
@@ -62,7 +62,7 @@ body: |
bb.0.entry:
liveins: $q0, $q1, $q2, $r0
- ; CHECK-LABEL: name: test_vminnmq_m_f32_v2
+ ; CHECK-LABEL: name: vpt_block_1_ins
; CHECK: liveins: $q0, $q1, $q2, $r0
; CHECK: $vpr = VMSR_P0 killed $r0, 14, $noreg
; CHECK: BUNDLE implicit-def $q0, implicit-def $d0, implicit-def $s0, implicit-def $s1, implicit-def $d1, implicit-def $s2, implicit-def $s3, implicit killed $vpr, implicit killed $q1, implicit killed $q2, implicit killed $q0 {
diff --git a/llvm/test/CodeGen/Thumb2/mve-vpt-block2.mir b/llvm/test/CodeGen/Thumb2/mve-vpt-block-2-ins.mir
similarity index 92%
rename from llvm/test/CodeGen/Thumb2/mve-vpt-block2.mir
rename to llvm/test/CodeGen/Thumb2/mve-vpt-block-2-ins.mir
index f69393ed6bd5..f106e8733371 100644
--- a/llvm/test/CodeGen/Thumb2/mve-vpt-block2.mir
+++ b/llvm/test/CodeGen/Thumb2/mve-vpt-block-2-ins.mir
@@ -5,7 +5,7 @@
target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
target triple = "thumbv8.1m.main-arm-none-eabi"
- define hidden arm_aapcs_vfpcc <4 x float> @test_vminnmq_m_f32_v2(<4 x float> %inactive1, <4 x float> %inactive2, <4 x float> %a, <4 x float> %b, i16 zeroext %p) local_unnamed_addr #0 {
+ define hidden arm_aapcs_vfpcc <4 x float> @vpt_block_2_ins(<4 x float> %inactive1, <4 x float> %inactive2, <4 x float> %a, <4 x float> %b, i16 zeroext %p) local_unnamed_addr #0 {
entry:
%conv.i = zext i16 %p to i32
%0 = tail call nnan ninf nsz <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float> %inactive1, <4 x float> %a, <4 x float> %b, i32 %conv.i) #2
@@ -14,7 +14,6 @@
}
declare <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float>, <4 x float>, <4 x float>, i32) #1
- declare void @llvm.stackprotector(i8*, i8**) #2
attributes #0 = { nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "denormal-fp-math"="preserve-sign" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="128" "frame-pointer"="none" "no-infs-fp-math"="true" "no-jump-tables"="false" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+armv8.1-m.main,+hwdiv,+mve.fp,+ras,+thumb-mode" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #1 = { nounwind readnone }
@@ -23,7 +22,7 @@
...
---
-name: test_vminnmq_m_f32_v2
+name: vpt_block_2_ins
alignment: 4
exposesReturnsTwice: false
legalized: false
@@ -65,7 +64,7 @@ body: |
bb.0.entry:
liveins: $q0, $q1, $q2, $q3, $r0
- ; CHECK-LABEL: name: test_vminnmq_m_f32_v2
+ ; CHECK-LABEL: name: vpt_block_2_ins
; CHECK: liveins: $q0, $q1, $q2, $q3, $r0
; CHECK: $vpr = VMSR_P0 killed $r0, 14, $noreg
; CHECK: BUNDLE implicit-def dead $q0, implicit-def $d0, implicit-def $s0, implicit-def $s1, implicit-def $d1, implicit-def $s2, implicit-def $s3, implicit-def $q1, implicit-def $d2, implicit-def $s4, implicit-def $s5, implicit-def $d3, implicit-def $s6, implicit-def $s7, implicit killed $vpr, implicit killed $q2, implicit killed $q3, implicit killed $q0, implicit killed $q1 {
diff --git a/llvm/test/CodeGen/Thumb2/mve-vpt-block3.mir b/llvm/test/CodeGen/Thumb2/mve-vpt-block-4-ins.mir
similarity index 93%
rename from llvm/test/CodeGen/Thumb2/mve-vpt-block3.mir
rename to llvm/test/CodeGen/Thumb2/mve-vpt-block-4-ins.mir
index 0fb22743061b..ee740a0fd3f9 100644
--- a/llvm/test/CodeGen/Thumb2/mve-vpt-block3.mir
+++ b/llvm/test/CodeGen/Thumb2/mve-vpt-block-4-ins.mir
@@ -5,7 +5,7 @@
target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
target triple = "thumbv8.1m.main-arm-none-eabi"
- define hidden arm_aapcs_vfpcc <4 x float> @test_vminnmq_m_f32_v2(<4 x float> %inactive1, <4 x float> %inactive2, <4 x float> %a, <4 x float> %b, i16 zeroext %p) local_unnamed_addr #0 {
+ define hidden arm_aapcs_vfpcc <4 x float> @vpt_block_4_ins(<4 x float> %inactive1, <4 x float> %inactive2, <4 x float> %a, <4 x float> %b, i16 zeroext %p) local_unnamed_addr #0 {
entry:
%conv.i = zext i16 %p to i32
%0 = tail call nnan ninf nsz <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float> undef, <4 x float> %a, <4 x float> %b, i32 %conv.i) #2
@@ -16,7 +16,6 @@
}
declare <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float>, <4 x float>, <4 x float>, i32) #1
- declare void @llvm.stackprotector(i8*, i8**) #2
attributes #0 = { nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "denormal-fp-math"="preserve-sign" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="128" "frame-pointer"="none" "no-infs-fp-math"="true" "no-jump-tables"="false" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+armv8.1-m.main,+hwdiv,+mve.fp,+ras,+thumb-mode" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #1 = { nounwind readnone }
@@ -24,7 +23,7 @@
...
---
-name: test_vminnmq_m_f32_v2
+name: vpt_block_4_ins
alignment: 4
exposesReturnsTwice: false
legalized: false
@@ -66,7 +65,7 @@ body: |
bb.0.entry:
liveins: $q0, $q1, $q2, $q3, $r0
- ; CHECK-LABEL: name: test_vminnmq_m_f32_v2
+ ; CHECK-LABEL: name: vpt_block_4_ins
; CHECK: liveins: $q0, $q1, $q2, $q3, $r0
; CHECK: $vpr = VMSR_P0 killed $r0, 14, $noreg
; CHECK: BUNDLE implicit-def dead $q2, implicit-def $d4, implicit-def $s8, implicit-def $s9, implicit-def $d5, implicit-def $s10, implicit-def $s11, implicit-def dead $q0, implicit-def $d0, implicit-def $s0, implicit-def $s1, implicit-def $d1, implicit-def $s2, implicit-def $s3, implicit-def $q1, implicit-def $d2, implicit-def $s4, implicit-def $s5, implicit-def $d3, implicit-def $s6, implicit-def $s7, implicit killed $vpr, implicit killed $q2, implicit killed $q3, implicit killed $q0, implicit killed $q1 {
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