[PATCH] D72310: [mlir][VectorOps] Implement strided_slice conversion

[Nicolas Vasilache via Phabricator via llvm-commits]

nicolasvasilache created this revision.
nicolasvasilache added reviewers: ftynse, rriddle.
Herald added subscribers: llvm-commits, lucyrfox, mgester, arpith-jacob, antiagainst, shauheen, burmako, jpienaar, mehdi_amini.
Herald added a project: LLVM.

This diff implements the progressive lowering of strided_slice to either:

1. extractelement + insertelement for the 1-D case
2. extract + optional strided_slice + insert for the n-D case.

This combines properly with the other conversion patterns to lower all the way to LLVM.

Appropriate tests are added.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D72310

Files:
  mlir/include/mlir/IR/Attributes.h
  mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp
  mlir/test/Conversion/VectorToLLVM/vector-to-llvm.mlir

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