[PATCH] D71929: AMDGPU/GlobalISel: Refine SMRD selection rules

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp:414
+  // There are no extending SMRD/SMEM loads, and they require 4-byte alignment.
   return MMO->getSize() >= 4 && MMO->getAlignment() >= 4 &&
+    // Can't do a scalar atomic load.
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arsenm wrote:
> rampitec wrote:
> > '(MMO->getSize() % 4) == 0'? What if we need 6 bytes, like v3i16?
> If it was legal, the alignment is high enough
Not necessarily, a vload() may result in underaligned loads. Also we cannot really load a subdword even if aligned, we would need to zero/sign extend it manually.


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  https://reviews.llvm.org/D71929/new/

https://reviews.llvm.org/D71929