[PATCH] D71929: AMDGPU/GlobalISel: Refine SMRD selection rules

Stanislav Mekhanoshin via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Jan 2 10:49:51 PST 2020


rampitec added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp:414
+  // There are no extending SMRD/SMEM loads, and they require 4-byte alignment.
   return MMO->getSize() >= 4 && MMO->getAlignment() >= 4 &&
+    // Can't do a scalar atomic load.
----------------
'(MMO->getSize() % 4) == 0'? What if we need 6 bytes, like v3i16?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D71929/new/

https://reviews.llvm.org/D71929





More information about the llvm-commits mailing list