[llvm] a36a89d - [NFC] Style cleanup

[Shengchen Kan via llvm-commits]

Author: Shengchen Kan
Date: 2019-12-31T16:10:36+08:00
New Revision: a36a89dcdcfc70de09693e62939009aaa0e52dd5

URL: https://github.com/llvm/llvm-project/commit/a36a89dcdcfc70de09693e62939009aaa0e52dd5
DIFF: https://github.com/llvm/llvm-project/commit/a36a89dcdcfc70de09693e62939009aaa0e52dd5.diff

LOG:  [NFC] Style cleanup

1. make function Is16BitMemOperand static
2. Use Doxygen features in comment
3. Rename functions to make them start with a lower case letter

Added: 
    

Modified: 
    llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
index 24f0f2b66ba8..c8c4046ee390 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
@@ -52,27 +52,6 @@ class X86MCCodeEmitter : public MCCodeEmitter {
                          const MCSubtargetInfo &STI) const override;
 
 private:
-  /// \param Op operand # of the memory operand.
-  ///
-  /// \returns true if the specified instruction has a 16-bit memory operand.
-  bool Is16BitMemOperand(const MCInst &MI, unsigned Op,
-                         const MCSubtargetInfo &STI) const {
-    const MCOperand &BaseReg = MI.getOperand(Op + X86::AddrBaseReg);
-    const MCOperand &IndexReg = MI.getOperand(Op + X86::AddrIndexReg);
-    const MCOperand &Disp = MI.getOperand(Op + X86::AddrDisp);
-
-    if (STI.hasFeature(X86::Mode16Bit) && BaseReg.getReg() == 0 &&
-        Disp.isImm() && Disp.getImm() < 0x10000)
-      return true;
-    if ((BaseReg.getReg() != 0 &&
-         X86MCRegisterClasses[X86::GR16RegClassID].contains(
-             BaseReg.getReg())) ||
-        (IndexReg.getReg() != 0 &&
-         X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg.getReg())))
-      return true;
-    return false;
-  }
-
   unsigned getX86RegNum(const MCOperand &MO) const {
     return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg()) & 0x7;
   }
@@ -192,8 +171,29 @@ static MCFixupKind getImmFixupKind(uint64_t TSFlags) {
   return MCFixup::getKindForSize(Size, isPCRel);
 }
 
+/// \param Op operand # of the memory operand.
+///
+/// \returns true if the specified instruction has a 16-bit memory operand.
+static bool is16BitMemOperand(const MCInst &MI, unsigned Op,
+                              const MCSubtargetInfo &STI) {
+  const MCOperand &BaseReg = MI.getOperand(Op + X86::AddrBaseReg);
+  const MCOperand &IndexReg = MI.getOperand(Op + X86::AddrIndexReg);
+  const MCOperand &Disp = MI.getOperand(Op + X86::AddrDisp);
+
+  if (STI.hasFeature(X86::Mode16Bit) && BaseReg.getReg() == 0 && Disp.isImm() &&
+      Disp.getImm() < 0x10000)
+    return true;
+  if ((BaseReg.getReg() != 0 &&
+       X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg.getReg())) ||
+      (IndexReg.getReg() != 0 &&
+       X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg.getReg())))
+    return true;
+  return false;
+}
+
+/// \param Op operand # of the memory operand.
+///
 /// \returns true if the specified instruction has a 32-bit memory operand.
-/// Op specifies the operand # of the memoperand.
 static bool is32BitMemOperand(const MCInst &MI, unsigned Op) {
   const MCOperand &BaseReg = MI.getOperand(Op + X86::AddrBaseReg);
   const MCOperand &IndexReg = MI.getOperand(Op + X86::AddrIndexReg);
@@ -212,8 +212,9 @@ static bool is32BitMemOperand(const MCInst &MI, unsigned Op) {
   return false;
 }
 
-/// \returns true if the specified instruction has
-/// a 64-bit memory operand. Op specifies the operand # of the memoperand.
+/// \param Op operand # of the memory operand.
+///
+/// \returns true if the specified instruction has a 64-bit memory operand.
 #ifndef NDEBUG
 static bool is64BitMemOperand(const MCInst &MI, unsigned Op) {
   const MCOperand &BaseReg = MI.getOperand(Op + X86::AddrBaseReg);
@@ -426,7 +427,7 @@ void X86MCCodeEmitter::emitMemModRMByte(const MCInst &MI, unsigned Op,
 
   // 16-bit addressing forms of the ModR/M byte have a 
diff erent encoding for
   // the R/M field and are far more limited in which registers can be used.
-  if (Is16BitMemOperand(MI, Op, STI)) {
+  if (is16BitMemOperand(MI, Op, STI)) {
     if (BaseReg) {
       // For 32-bit addressing, the row and column values in Table 2-2 are
       // basically the same. It's AX/CX/DX/BX/SP/BP/SI/DI in that order, with
@@ -1303,15 +1304,15 @@ void X86MCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
   } else if (MemoryOperand < 0) {
     need_address_override = false;
   } else if (STI.hasFeature(X86::Mode64Bit)) {
-    assert(!Is16BitMemOperand(MI, MemoryOperand, STI));
+    assert(!is16BitMemOperand(MI, MemoryOperand, STI));
     need_address_override = is32BitMemOperand(MI, MemoryOperand);
   } else if (STI.hasFeature(X86::Mode32Bit)) {
     assert(!is64BitMemOperand(MI, MemoryOperand));
-    need_address_override = Is16BitMemOperand(MI, MemoryOperand, STI);
+    need_address_override = is16BitMemOperand(MI, MemoryOperand, STI);
   } else {
     assert(STI.hasFeature(X86::Mode16Bit));
     assert(!is64BitMemOperand(MI, MemoryOperand));
-    need_address_override = !Is16BitMemOperand(MI, MemoryOperand, STI);
+    need_address_override = !is16BitMemOperand(MI, MemoryOperand, STI);
   }
 
   if (need_address_override)