[PATCH] D71921: [PowerPC] Use isPredicable bits in instruction definitions

[Jinsong Ji via Phabricator via llvm-commits]

jsji added a comment.



> I checked all references to `isPredicable` in codebase:
> 
> - Instr doc generation uses the bit (this is non-functional)
> - CodeGen tablegen itself uses it
> - Both `TargetInstrInfo::isUnpredicatedTerminator` and `TargetInstrInfo::PredicateInstruction` references the method, but PPC overrides them and doesn't use it.
> - `MachineInstr::findFirstPredOperandIdx` references it, but only ARM and AMDGPU invokes it
> - Implicit null check <https://github.com/llvm/llvm-project/blob/266cd7717c8126213a7560d26da5495053be90c0/llvm/lib/CodeGen/ImplicitNullChecks.cpp#L375> and machine sink <https://github.com/llvm/llvm-project/blob/266cd7717c8126213a7560d26da5495053be90c0/llvm/lib/CodeGen/MachineSink.cpp#L773> have referenced it. However, this patch won't touch instrs may load or store, so result of expression would never change
> - Other references are for other platforms

So, I assume you are saying this is *NFC* for PowerPC, right?


Repository:
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https://reviews.llvm.org/D71921