[llvm] 18240c3 - AMDGPU/GlobalISel: Add select test for fexp2

[Matt Arsenault via llvm-commits]

Author: Matt Arsenault
Date: 2019-12-30T10:56:37-05:00
New Revision: 18240c3cd632521f95f2ddd08ecc4f7cf0efe3c8

URL: https://github.com/llvm/llvm-project/commit/18240c3cd632521f95f2ddd08ecc4f7cf0efe3c8
DIFF: https://github.com/llvm/llvm-project/commit/18240c3cd632521f95f2ddd08ecc4f7cf0efe3c8.diff

LOG: AMDGPU/GlobalISel: Add select test for fexp2

Added: 
    llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fexp2.mir

Modified: 
    

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fexp2.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fexp2.mir
new file mode 100644
index 000000000000..bb2ba24d411c
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fexp2.mir
@@ -0,0 +1,42 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: fexp2_s32_vs
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0
+
+    ; CHECK-LABEL: name: fexp2_s32_vs
+    ; CHECK: liveins: $sgpr0
+    ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+    ; CHECK: [[V_EXP_F32_e64_:%[0-9]+]]:vgpr_32 = V_EXP_F32_e64 0, [[COPY]], 0, 0, implicit $exec
+    ; CHECK: S_ENDPGM 0, implicit [[V_EXP_F32_e64_]]
+    %0:sgpr(s32) = COPY $sgpr0
+    %1:vgpr(s32) = G_FEXP2 %0
+    S_ENDPGM 0, implicit %1
+...
+
+---
+name: fexp2_s32_vv
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    liveins: $vgpr0
+
+    ; CHECK-LABEL: name: fexp2_s32_vv
+    ; CHECK: liveins: $vgpr0
+    ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; CHECK: [[V_EXP_F32_e64_:%[0-9]+]]:vgpr_32 = V_EXP_F32_e64 0, [[COPY]], 0, 0, implicit $exec
+    ; CHECK: S_ENDPGM 0, implicit [[V_EXP_F32_e64_]]
+    %0:vgpr(s32) = COPY $vgpr0
+    %1:vgpr(s32) = G_FEXP2 %0
+    S_ENDPGM 0, implicit %1
+...