[PATCH] D71921: [PowerPC] Use isPredicable bits in instruction definitions

[qshanz via Phabricator via llvm-commits]

steven.zhang added a comment.

You need to revisit the place that use the isPredicable bit of the MI, which might cause functionality change. i.e.

  bool TargetInstrInfo::isUnpredicatedTerminator(const MachineInstr &MI) const {
    if (!MI.isTerminator()) return false;
  
    // Conditional branch is a special case.
    if (MI.isBranch() && !MI.isBarrier())
      return true;
    if (!MI.isPredicable())
      return true;
    return !isPredicated(MI);
  }
  
  bool TargetInstrInfo::PredicateInstruction(
      MachineInstr &MI, ArrayRef<MachineOperand> Pred) const {
    bool MadeChange = false;
  
    assert(!MI.isBundle() &&
           "TargetInstrInfo::PredicateInstruction() can't handle bundles");
  
    const MCInstrDesc &MCID = MI.getDesc();
    if (!MI.isPredicable())
      return false;
  
    for (unsigned j = 0, i = 0, e = MI.getNumOperands(); i != e; ++i) {
      if (MCID.OpInfo[i].isPredicate()) {
        MachineOperand &MO = MI.getOperand(i);
        if (MO.isReg()) {
          MO.setReg(Pred[j].getReg());
          MadeChange = true;
        } else if (MO.isImm()) {
          MO.setImm(Pred[j].getImm());
          MadeChange = true;
        } else if (MO.isMBB()) {
          MO.setMBB(Pred[j].getMBB());
          MadeChange = true;
        }
        ++j;
      }
    }
    return MadeChange;
  }


Repository:
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  https://reviews.llvm.org/D71921/new/

https://reviews.llvm.org/D71921