[llvm] dc03b96 - Add parentheses to silence warning

[Florian Hahn via llvm-commits]

> On Dec 20, 2019, at 21:52, Bill Wendling via llvm-commits <llvm-commits at lists.llvm.org> wrote:
> 
> 
> Author: Bill Wendling
> Date: 2019-12-20T12:52:36-08:00
> New Revision: dc03b960d0236c18ed4382cea7bb3eb49329ed04
> 
> URL: https://github.com/llvm/llvm-project/commit/dc03b960d0236c18ed4382cea7bb3eb49329ed04
> DIFF: https://github.com/llvm/llvm-project/commit/dc03b960d0236c18ed4382cea7bb3eb49329ed04.diff
> 
> LOG: Add parentheses to silence warning
> 
> Added: 
> 
> 
> Modified: 
>    llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
> 
> Removed: 
> 
> 
> 
> ################################################################################
> diff  --git a/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp b/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
> index d24e6d63f157..f2ff26ee0780 100644
> --- a/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
> +++ b/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
> @@ -831,8 +831,8 @@ AArch64LoadStoreOpt::mergePairedInsns(MachineBasicBlock::iterator I,
>             for (auto &MOP : MI.operands()) {
>               if (MOP.isReg() && !MOP.isDebug() && MOP.getReg() &&
>                   TRI->regsOverlap(MOP.getReg(), RegToRename)) {
> -                assert(MOP.isImplicit() ||
> -                       (MOP.isRenamable() && !MOP.isEarlyClobber()) &&
> +                assert((MOP.isImplicit() ||
> +                        (MOP.isRenamable() && !MOP.isEarlyClobber())) &&
>                            "Need renamable operands");
>                 MOP.setReg(GetMatchingSubReg(MOP.getReg()));
>               }
> 


Thanks!