[PATCH] D71698: [AArch64][SVE] Add intrinsic for non-faulting loads

[Kerry McLaughlin via Phabricator via llvm-commits]

kmclaughlin added inline comments.


================
Comment at: llvm/lib/Target/AArch64/SVEInstrFormats.td:5333
+  // We need a layer of indirection because early machine code passes balk at
+  // physical register (i.e. FFR) uses that have no previous definition.
+  let hasSideEffects = 1, hasNoSchedulingInfo = 1, mayLoad = 1 in {
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efriedma wrote:
> This is depending on hasSideEffects to preserve the correct ordering with instructions that read/write FFR?  That probably works.  I guess the alternative is to insert an IMPLICIT_DEF of FFR in the entry block of each function.
> 
> What are the calling convention rules for FFR?  Is it callee-save?  If not, we might need to do some work to make FFR reads/writes do something sane across calls inserted by the compiler.
The FFR is not callee-saved. We will need to add support to save & restore it where appropriate at the point the compiler starts generating reads to the FFR, but for the purpose of the ACLE the user will be required to do this if necessary.


Repository:
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  https://reviews.llvm.org/D71698/new/

https://reviews.llvm.org/D71698