[PATCH] D71767: [POC][SVE] Allow code generation for fixed length vectorised loops [Patch 2/2].

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm created this revision.
Herald added subscribers: llvm-commits, psnobl, rkruppe, hiraditya, kristof.beyls, tschuett.
Herald added a reviewer: rengolin.
Herald added a reviewer: efriedma.
Herald added a project: LLVM.

No expectations for review at this stage unless you are super keen.

This extends the proof of concept introduced by https://reviews.llvm.org/D71760 to show the work required to custom lower the main fixed length vector operations.  The general scheme being:

  <n x ty> op (<n x ty> op1, <n x ty> op2...

becomes

  pg = create_predicate_for(<n x ty>)
  new_op1 = convertToSVE(op1)
  new_op2 = convertToSVE(op2)
  ...
  return convertFromSVE(sve_op(pg, new_op1, new_op2...

To keep the patch small I've reused the existing intrinsic isel rules.  This provides a route to reasonable performance whilst allowing us to start work on immediate packing, condition code handling and better utilisation of reversed instructions and movprfx.  The ultimately goal is that the first patch ensures everything can run, whilst this and subsequent patches improve performance.

WARNING: The more operations we lower the more existing code paths will need to be cleaned so they no longer assume that (isTypeLegal(VectorType) implies VectorType.getSizeInBits() >= 128).  This can be seen in this patch which required a charge to one of the AArch64 DAGCombines.




https://reviews.llvm.org/D71767

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/SVEInstrFormats.td

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