[PATCH] D71760: [POC][SVE] Allow code generation for fixed length vectorised loops [Patch 1/2].

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm created this revision.
Herald added subscribers: llvm-commits, psnobl, rkruppe, hiraditya, tschuett.
Herald added a reviewer: rengolin.
Herald added a reviewer: efriedma.
Herald added a project: LLVM.

This is a proof of concept patch to show how SVE can be used to code generate fixed length vectors.  It represents the minimum amount of SVE instructions (ld1, st1, uzp, uunpklo) required to get most workloads to run.

The general idea is to make all fixed length vector types that fit within a user specified size legal and custom lower all fixed length vector operations to scalable vector operations that use a suitably created predicate.  After legalisation there should be no vector operations that operate on fixed length vectors beyond insert/extract_subvector and various extends and truncate.  The reason for special case these operations is to maximum our ability for DAG combine to remove them.  Those still around at isel get custom selected within ISelDagToDag.


https://reviews.llvm.org/D71760

Files:
  clang/include/clang/Driver/Options.td
  clang/lib/Driver/ToolChains/Clang.cpp
  llvm/include/llvm/CodeGen/ValueTypes.h
  llvm/include/llvm/Support/MachineValueType.h
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
  llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/lib/Target/AArch64/AArch64Subtarget.cpp
  llvm/lib/Target/AArch64/AArch64Subtarget.h
  llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h

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