[llvm] d3aeac8 - [PowerPC] Only use PLT annotations if using PIC relocation model
Justin Hibbits via llvm-commits
llvm-commits at lists.llvm.org
Thu Dec 19 07:31:15 PST 2019
Author: Justin Hibbits
Date: 2019-12-19T09:27:13-06:00
New Revision: d3aeac8e20fb3714eb69d6ed5838d57c7ddcd8e8
URL: https://github.com/llvm/llvm-project/commit/d3aeac8e20fb3714eb69d6ed5838d57c7ddcd8e8
DIFF: https://github.com/llvm/llvm-project/commit/d3aeac8e20fb3714eb69d6ed5838d57c7ddcd8e8.diff
LOG: [PowerPC] Only use PLT annotations if using PIC relocation model
Summary:
The default static (non-PIC, non-PIE) model for 32-bit powerpc does not
use @PLT annotations and relocations in GCC. LLVM shouldn't use @PLT
annotations either, because it breaks secure-PLT linking with (some
versions of?) GNU LD.
Update the available-externally.ll test to reflect that default mode should be
the same as the static relocation, by using the same check prefix.
Reviewed by: sfertile
Differential Revision: https://reviews.llvm.org/D70570
Added:
Modified:
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/test/CodeGen/PowerPC/2008-10-28-f128-i32.ll
llvm/test/CodeGen/PowerPC/2010-02-12-saveCR.ll
llvm/test/CodeGen/PowerPC/available-externally.ll
llvm/test/CodeGen/PowerPC/srem-lkk.ll
llvm/test/CodeGen/PowerPC/stubs.ll
llvm/test/CodeGen/PowerPC/umulo-128-legalisation-lowering.ll
llvm/test/CodeGen/PowerPC/urem-lkk.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 899a4f6f8466..3062dbb655f8 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -5107,7 +5107,13 @@ static SDValue transformCallee(const SDValue &Callee, SelectionDAG &DAG,
G ? G->getGlobal() : nullptr);
};
- bool UsePlt = Subtarget.is32BitELFABI() && !isLocalCallee();
+ // The PLT is only used in 32-bit ELF PIC mode. Attempting to use the PLT in
+ // a static relocation model causes some versions of GNU LD (2.17.50, at
+ // least) to force BSS-PLT, instead of secure-PLT, even if all objects are
+ // built with secure-PLT.
+ bool UsePlt =
+ Subtarget.is32BitELFABI() && !isLocalCallee() &&
+ Subtarget.getTargetMachine().getRelocationModel() == Reloc::PIC_;
if (isFunctionGlobalAddress(Callee)) {
const GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Callee);
diff --git a/llvm/test/CodeGen/PowerPC/2008-10-28-f128-i32.ll b/llvm/test/CodeGen/PowerPC/2008-10-28-f128-i32.ll
index c851e73b1f1f..7897d1c6b8a5 100644
--- a/llvm/test/CodeGen/PowerPC/2008-10-28-f128-i32.ll
+++ b/llvm/test/CodeGen/PowerPC/2008-10-28-f128-i32.ll
@@ -62,7 +62,7 @@ define i64 @__fixunstfdi(ppc_fp128 %a) nounwind readnone {
; CHECK-NEXT: stw 3, 312(1)
; CHECK-NEXT: lfd 30, 312(1)
; CHECK-NEXT: fmr 2, 30
-; CHECK-NEXT: bl __gcc_qmul at PLT
+; CHECK-NEXT: bl __gcc_qmul
; CHECK-NEXT: lis 3, 16864
; CHECK-NEXT: stfd 1, 280(1)
; CHECK-NEXT: stw 3, 368(1)
@@ -84,7 +84,7 @@ define i64 @__fixunstfdi(ppc_fp128 %a) nounwind readnone {
; CHECK-NEXT: lwz 3, 288(1)
; CHECK-NEXT: stw 3, 344(1)
; CHECK-NEXT: lfd 2, 344(1)
-; CHECK-NEXT: bl __gcc_qsub at PLT
+; CHECK-NEXT: bl __gcc_qsub
; CHECK-NEXT: mffs 0
; CHECK-NEXT: mtfsb1 31
; CHECK-NEXT: lis 3, .LCPI0_1 at ha
@@ -117,7 +117,7 @@ define i64 @__fixunstfdi(ppc_fp128 %a) nounwind readnone {
; CHECK-NEXT: .LBB0_5: # %bb1
; CHECK-NEXT: li 4, 0
; CHECK-NEXT: mr 3, 30
-; CHECK-NEXT: bl __floatditf at PLT
+; CHECK-NEXT: bl __floatditf
; CHECK-NEXT: lis 3, 17392
; CHECK-NEXT: stfd 1, 208(1)
; CHECK-NEXT: stw 3, 240(1)
@@ -140,7 +140,7 @@ define i64 @__fixunstfdi(ppc_fp128 %a) nounwind readnone {
; CHECK-NEXT: lwz 3, 200(1)
; CHECK-NEXT: stw 3, 216(1)
; CHECK-NEXT: lfd 2, 216(1)
-; CHECK-NEXT: bl __gcc_qadd at PLT
+; CHECK-NEXT: bl __gcc_qadd
; CHECK-NEXT: blt 2, .LBB0_7
; CHECK-NEXT: # %bb.6: # %bb1
; CHECK-NEXT: fmr 2, 28
@@ -163,7 +163,7 @@ define i64 @__fixunstfdi(ppc_fp128 %a) nounwind readnone {
; CHECK-NEXT: lwz 3, 192(1)
; CHECK-NEXT: stw 3, 248(1)
; CHECK-NEXT: lfd 4, 248(1)
-; CHECK-NEXT: bl __gcc_qsub at PLT
+; CHECK-NEXT: bl __gcc_qsub
; CHECK-NEXT: stfd 2, 176(1)
; CHECK-NEXT: stfd 1, 168(1)
; CHECK-NEXT: fcmpu 1, 2, 27
@@ -206,7 +206,7 @@ define i64 @__fixunstfdi(ppc_fp128 %a) nounwind readnone {
; CHECK-NEXT: lwz 3, 40(1)
; CHECK-NEXT: stw 3, 56(1)
; CHECK-NEXT: lfd 2, 56(1)
-; CHECK-NEXT: bl __gcc_qsub at PLT
+; CHECK-NEXT: bl __gcc_qsub
; CHECK-NEXT: mffs 0
; CHECK-NEXT: mtfsb1 31
; CHECK-NEXT: lis 3, .LCPI0_2 at ha
@@ -261,7 +261,7 @@ define i64 @__fixunstfdi(ppc_fp128 %a) nounwind readnone {
; CHECK-NEXT: lwz 3, 104(1)
; CHECK-NEXT: stw 3, 120(1)
; CHECK-NEXT: lfd 2, 120(1)
-; CHECK-NEXT: bl __gcc_qsub at PLT
+; CHECK-NEXT: bl __gcc_qsub
; CHECK-NEXT: mffs 0
; CHECK-NEXT: mtfsb1 31
; CHECK-NEXT: lis 3, .LCPI0_0 at ha
diff --git a/llvm/test/CodeGen/PowerPC/2010-02-12-saveCR.ll b/llvm/test/CodeGen/PowerPC/2010-02-12-saveCR.ll
index 995f6bd23163..238af20a25ab 100644
--- a/llvm/test/CodeGen/PowerPC/2010-02-12-saveCR.ll
+++ b/llvm/test/CodeGen/PowerPC/2010-02-12-saveCR.ll
@@ -11,7 +11,7 @@ entry:
; CHECK-DAG: ori [[T2:[0-9]+]], [[T2]], 34492
; CHECK-DAG: stwx [[T1]], 1, [[T2]]
; CHECK-DAG: addi 3, 1, 28
-; CHECK: bl bar at PLT
+; CHECK: bl bar
%x = alloca [100000 x i8] ; <[100000 x i8]*> [#uses=1]
%"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
%x1 = bitcast [100000 x i8]* %x to i8* ; <i8*> [#uses=1]
diff --git a/llvm/test/CodeGen/PowerPC/available-externally.ll b/llvm/test/CodeGen/PowerPC/available-externally.ll
index 51b972bd3d77..ec83c67993b5 100644
--- a/llvm/test/CodeGen/PowerPC/available-externally.ll
+++ b/llvm/test/CodeGen/PowerPC/available-externally.ll
@@ -1,3 +1,4 @@
+; RUN: llc -verify-machineinstrs < %s | FileCheck %s -check-prefix=STATIC
; RUN: llc -verify-machineinstrs < %s -relocation-model=static | FileCheck %s -check-prefix=STATIC
; RUN: llc -verify-machineinstrs < %s -relocation-model=pic -mtriple=powerpc-unknown-linux-gnu | FileCheck %s -check-prefix=PIC
; RUN: llc -verify-machineinstrs < %s -relocation-model=pic -mtriple=powerpc-unknown-linux | FileCheck %s -check-prefix=PICELF
@@ -14,7 +15,7 @@ target triple = "powerpc-unknown-linux-gnu"
define i32 @foo(i64 %x) nounwind {
entry:
; STATIC: foo:
-; STATIC: bl exact_log2 at PLT
+; STATIC: bl exact_log2
; STATIC: blr
; PIC: foo:
diff --git a/llvm/test/CodeGen/PowerPC/srem-lkk.ll b/llvm/test/CodeGen/PowerPC/srem-lkk.ll
index ccd1b612235a..97c9089f3986 100644
--- a/llvm/test/CodeGen/PowerPC/srem-lkk.ll
+++ b/llvm/test/CodeGen/PowerPC/srem-lkk.ll
@@ -139,7 +139,7 @@ define i64 @dont_fold_srem_i64(i64 %x) {
; CHECK-NEXT: .cfi_offset lr, 4
; CHECK-NEXT: li 5, 0
; CHECK-NEXT: li 6, 98
-; CHECK-NEXT: bl __moddi3 at PLT
+; CHECK-NEXT: bl __moddi3
; CHECK-NEXT: lwz 0, 20(1)
; CHECK-NEXT: addi 1, 1, 16
; CHECK-NEXT: mtlr 0
diff --git a/llvm/test/CodeGen/PowerPC/stubs.ll b/llvm/test/CodeGen/PowerPC/stubs.ll
index 33499f1bcaa7..d8772b9b7fa2 100644
--- a/llvm/test/CodeGen/PowerPC/stubs.ll
+++ b/llvm/test/CodeGen/PowerPC/stubs.ll
@@ -6,4 +6,4 @@ entry:
}
; CHECK: test1:
-; CHECK: bl __floatditf at PLT
+; CHECK: bl __floatditf
diff --git a/llvm/test/CodeGen/PowerPC/umulo-128-legalisation-lowering.ll b/llvm/test/CodeGen/PowerPC/umulo-128-legalisation-lowering.ll
index 9172bd02ec30..a6df2661d48a 100644
--- a/llvm/test/CodeGen/PowerPC/umulo-128-legalisation-lowering.ll
+++ b/llvm/test/CodeGen/PowerPC/umulo-128-legalisation-lowering.ll
@@ -63,7 +63,7 @@ define { i128, i8 } @muloti_test(i128 %l, i128 %r) unnamed_addr #0 {
; PPC32-NEXT: mr 28, 9
; PPC32-NEXT: mr 23, 6
; PPC32-NEXT: mr 24, 5
-; PPC32-NEXT: bl __multi3 at PLT
+; PPC32-NEXT: bl __multi3
; PPC32-NEXT: mr 7, 4
; PPC32-NEXT: mullw 4, 24, 30
; PPC32-NEXT: mullw 8, 29, 23
diff --git a/llvm/test/CodeGen/PowerPC/urem-lkk.ll b/llvm/test/CodeGen/PowerPC/urem-lkk.ll
index f361200d54fd..307af5ec3ae3 100644
--- a/llvm/test/CodeGen/PowerPC/urem-lkk.ll
+++ b/llvm/test/CodeGen/PowerPC/urem-lkk.ll
@@ -96,7 +96,7 @@ define i64 @dont_fold_urem_i64(i64 %x) {
; CHECK-NEXT: .cfi_offset lr, 4
; CHECK-NEXT: li 5, 0
; CHECK-NEXT: li 6, 98
-; CHECK-NEXT: bl __umoddi3 at PLT
+; CHECK-NEXT: bl __umoddi3
; CHECK-NEXT: lwz 0, 20(1)
; CHECK-NEXT: addi 1, 1, 16
; CHECK-NEXT: mtlr 0
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