[PATCH] D71655: [MachineScheduler] Allow clustering mem ops with complex addresses

[Jay Foad via Phabricator via llvm-commits]

foad created this revision.
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The generic BaseMemOpClusterMutation calls into TargetInstrInfo to
analyze the address of each load/store instruction, and again to decide
whether two instructions should be clustered. Previously this had to
represent each address as a base operand plus a constant offset. This
patch extends it to support addresses composed from any number of
operands, e.g. basereg + indexreg + offset.

The old target hook TargetInstrInfo::getMemOperandWithOffset has been
renamed and split into three:

getMemBaseRegWithOffset: returns a base register plus byte offset,
default implementation calls...

getMemBaseOpWithOffset: returns a base operand (register or frame index)
plus byte offset, default implementation calls...

getMemAddressOperands: returns one or more operands, with the only
requirements being:

- they can be sorted by MemOpInfo::Compare, such that clusterable ops get sorted next to each other, and
- TargetInstrInfo::shouldClusterMemOps knows what they mean.

Targets that want clustering should implement the most general hook,
getMemAddressOperands. Other targets can get away with implementing one
of the more specific hooks.

One simple follow-on is to enable clustering of AMDGPU FLAT instructions
with both vaddr and saddr (base register + offset register). I've left
a FIXME in the code for this case.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D71655

Files:
  llvm/include/llvm/CodeGen/TargetInstrInfo.h
  llvm/lib/CodeGen/ImplicitNullChecks.cpp
  llvm/lib/CodeGen/MachinePipeliner.cpp
  llvm/lib/CodeGen/MachineScheduler.cpp
  llvm/lib/CodeGen/MachineSink.cpp
  llvm/lib/CodeGen/ModuloSchedule.cpp
  llvm/lib/CodeGen/TargetInstrInfo.cpp
  llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
  llvm/lib/Target/AArch64/AArch64InstrInfo.h
  llvm/lib/Target/AArch64/AArch64StorePairSuppress.cpp
  llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
  llvm/lib/Target/AMDGPU/SIInstrInfo.h
  llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp
  llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
  llvm/lib/Target/Hexagon/HexagonInstrInfo.h
  llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
  llvm/lib/Target/Lanai/LanaiInstrInfo.cpp
  llvm/lib/Target/Lanai/LanaiInstrInfo.h
  llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
  llvm/lib/Target/PowerPC/PPCInstrInfo.h
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfo.h
  llvm/lib/Target/X86/X86InstrInfo.cpp
  llvm/lib/Target/X86/X86InstrInfo.h
  llvm/test/CodeGen/AMDGPU/ds_read2st64.ll

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