[PATCH] D71515: [AArch64] match fcvtl2 with bitcasted extract

[Sanjay Patel via Phabricator via llvm-commits]

spatel updated this revision to Diff 234310.
spatel edited the summary of this revision.
spatel added a comment.

Patch updated:

1. Added tests for other casts and half->float. (rGfbaf835c5c51 <https://reviews.llvm.org/rGfbaf835c5c515bf00dccd880b8afe0b2e0a10e06>)
2. Add a helper to AArch64DAGToDAGISel to deal with all high half extend possibilities.
3. Remove redundant tablegen patterns for fcvtl2.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D71515/new/

https://reviews.llvm.org/D71515

Files:
  llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/test/CodeGen/AArch64/arm64-vcvt_f.ll

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