[llvm] e7f585e - PostRA Machine Sink should take care of COPY defining register that is a sub-register by another COPY source operand

[via llvm-commits]

Author: alex-t
Date: 2019-12-17T15:20:43+03:00
New Revision: e7f585ed6109b1f20131b91af87e3c2ae1e59616

URL: https://github.com/llvm/llvm-project/commit/e7f585ed6109b1f20131b91af87e3c2ae1e59616
DIFF: https://github.com/llvm/llvm-project/commit/e7f585ed6109b1f20131b91af87e3c2ae1e59616.diff

LOG: PostRA Machine Sink should take care of COPY defining register that is a sub-register by another COPY source operand

Differential Revision: https://reviews.llvm.org/D71132

Added: 
    llvm/test/CodeGen/AMDGPU/postra-machine-sink.mir

Modified: 
    llvm/lib/CodeGen/MachineSink.cpp
    llvm/test/CodeGen/AArch64/bisect-post-ra-machine-sink.mir
    llvm/test/CodeGen/AArch64/post-ra-machine-sink.mir

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/MachineSink.cpp b/llvm/lib/CodeGen/MachineSink.cpp
index 6900c195e0e1..a4ba197b7a1d 100644
--- a/llvm/lib/CodeGen/MachineSink.cpp
+++ b/llvm/lib/CodeGen/MachineSink.cpp
@@ -1215,10 +1215,14 @@ static void updateLiveIn(MachineInstr *MI, MachineBasicBlock *SuccBB,
     for (MCSubRegIterator S(DefReg, TRI, true); S.isValid(); ++S)
       SuccBB->removeLiveIn(*S);
   for (auto U : UsedOpsInCopy) {
-    Register Reg = MI->getOperand(U).getReg();
-    if (!SuccBB->isLiveIn(Reg))
-      SuccBB->addLiveIn(Reg);
+    Register SrcReg = MI->getOperand(U).getReg();
+    LaneBitmask Mask;
+    for (MCRegUnitMaskIterator S(SrcReg, TRI); S.isValid(); ++S) {
+      Mask |= (*S).second;
+    }
+    SuccBB->addLiveIn(SrcReg, Mask.any() ? Mask : LaneBitmask::getAll());
   }
+  SuccBB->sortUniqueLiveIns();
 }
 
 static bool hasRegisterDependency(MachineInstr *MI,

diff  --git a/llvm/test/CodeGen/AArch64/bisect-post-ra-machine-sink.mir b/llvm/test/CodeGen/AArch64/bisect-post-ra-machine-sink.mir
index 4128e7c80ff3..15c1ccb0e609 100644
--- a/llvm/test/CodeGen/AArch64/bisect-post-ra-machine-sink.mir
+++ b/llvm/test/CodeGen/AArch64/bisect-post-ra-machine-sink.mir
@@ -9,7 +9,7 @@
 # RUN-POSTRA: bb.0:
 # RUN-POSTRA-NOT: $w19 = COPY killed $w0
 # RUN-POSTRA: bb.1:
-# RUN-POSTRA: liveins: $w1, $w0
+# RUN-POSTRA: liveins: $w0, $w1
 # RUN-POSTRA: renamable $w19 = COPY killed $w0
 
 # Make sure the pass it not run.

diff  --git a/llvm/test/CodeGen/AArch64/post-ra-machine-sink.mir b/llvm/test/CodeGen/AArch64/post-ra-machine-sink.mir
index ca9e9f6c1c69..c40af3b042ca 100644
--- a/llvm/test/CodeGen/AArch64/post-ra-machine-sink.mir
+++ b/llvm/test/CodeGen/AArch64/post-ra-machine-sink.mir
@@ -6,7 +6,7 @@
 # CHECK-LABEL: bb.0:
 # CHECK-NOT: $w19 = COPY killed $w0
 # CHECK-LABEL: bb.1:
-# CHECK: liveins: $w1, $w0
+# CHECK: liveins: $w0, $w1
 # CHECK: renamable $w19 = COPY killed $w0
 
 name: sinkcopy1
@@ -35,7 +35,7 @@ body: |
 # CHECK-LABEL: bb.0:
 # CHECK-NOT: renamable $w19 = COPY killed $w0
 # CHECK-LABEL: bb.2:
-# CHECK: liveins: $w1, $w0
+# CHECK: liveins: $w0, $w1
 # CHECK: renamable $w19 = COPY killed $w0
 name: sinkcopy2
 tracksRegLiveness: true
@@ -63,7 +63,7 @@ body: |
 # CHECK-LABEL: bb.0:
 # CHECK-NOT: renamable $w19 = COPY killed $w0
 # CHECK-LABEL: bb.1:
-# CHECK: liveins: $w1, $w0
+# CHECK: liveins: $w0, $w1
 # CHECK: renamable $w19 = COPY killed $w0
 # CHECK: renamable $w20 = COPY killed $w1
 name: sinkcopy3
@@ -89,7 +89,7 @@ body: |
 # CHECK-NOT: renamable $w19 = COPY killed $w0
 # CHECK-NOT: renamable $w20 = COPY killed $w1
 # CHECK-LABEL: bb.1:
-# CHECK: liveins: $w1, $w0
+# CHECK: liveins: $w0, $w1
 # CHECK: renamable $w19 = COPY killed $w0
 # CHECK-LABEL: bb.2:
 # CHECK: liveins: $w0, $w1
@@ -123,7 +123,7 @@ body: |
 # CHECK-LABEL: bb.2:
 # CHECK: $w1 = ADDWrr $w1, $w0
 # CHECK-LABEL: bb.3:
-# CHECK: liveins: $w1, $w0
+# CHECK: liveins: $w0, $w1
 # CHECK: renamable $w19 = COPY killed $w0
 name: sinkcopy5
 tracksRegLiveness: true
@@ -155,7 +155,7 @@ body: |
 # CHECK-NOT: renamable $w19 = COPY $w0
 # CHECK-NOT: renamable $w20 = COPY $w0
 # CHECK-LABEL: bb.2:
-# CHECK: liveins: $w1, $w0
+# CHECK: liveins: $w0, $w1
 # CHECK: renamable $w19 = COPY $w0
 # CHECK: renamable $w20 = COPY $w19
 name: sinkcopy6
@@ -213,7 +213,7 @@ body: |
 # CHECK-LABEL: bb.2:
 # CHECK: $w1 = ADDWrr $w1, $w0, implicit $x0
 # CHECK-LABEL: bb.3:
-# CHECK: liveins: $x1, $w0
+# CHECK: liveins: $w0, $x1
 # CHECK: renamable $w19 = COPY killed $w0, implicit-def $x19
 name: sinkcopy8
 tracksRegLiveness: true

diff  --git a/llvm/test/CodeGen/AMDGPU/postra-machine-sink.mir b/llvm/test/CodeGen/AMDGPU/postra-machine-sink.mir
new file mode 100644
index 000000000000..b034cae99260
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/postra-machine-sink.mir
@@ -0,0 +1,31 @@
+# RUN: llc -march=amdgcn -mcpu=gfx908 -run-pass=postra-machine-sink -verify-machineinstrs -o - %s | FileCheck %s
+
+# Don't sink copy that writes sub-register of another copy source register
+# CHECK-LABEL: name: donotsinkcopy
+# CHECK-LABEL: bb.0:
+# CHECK: renamable $sgpr1 = COPY renamable $sgpr2
+# CHECK-LABEL: bb.1:
+# CHECK: liveins: $sgpr0_sgpr1:0x00000003
+# CHECK: renamable $vgpr1_vgpr2 = COPY renamable $sgpr0_sgpr1
+
+---
+name: donotsinkcopy
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: $sgpr0, $sgpr2, $vgpr3
+    S_CMP_LT_U32 renamable $sgpr2, target-flags(amdgpu-gotprel32-lo) 2, implicit-def $scc
+    renamable $sgpr1 = COPY renamable $sgpr2
+    renamable $vgpr1_vgpr2 = COPY renamable $sgpr0_sgpr1
+    S_CBRANCH_SCC0 %bb.2, implicit $scc
+
+  bb.1:
+    liveins: $vgpr2, $sgpr0_sgpr1:0x00000001
+    S_BRANCH %bb.4
+
+  bb.2:
+    liveins: $sgpr1
+
+  bb.4:
+   S_ENDPGM 0
+...