[PATCH] D69483: [PowerPC]: Fix predicate handling with SPE

[Jim Lin via Phabricator via llvm-commits]

Jim added a comment.

A few nits.
You can use git-clang-format to format your patch for following llvm coding style.



================
Comment at: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:3869
+  switch (CC) {
+    case ISD::SETOEQ:
+    case ISD::SETEQ:
----------------
It doesn't need indentation for case.
It should look like:
```
switch (CC) {
case ISD::SETOEQ:
...
```


================
Comment at: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:4926
+        (N->getOperand(0).getValueType() == MVT::f64 ||
+	 N->getOperand(0).getValueType() == MVT::f32))
+      BROpc = getPredicateForSetCCForSPE(CC);
----------------
It looks weird. Does it use tab as indentation?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D69483/new/

https://reviews.llvm.org/D69483