[PATCH] D71390: [PowerPC] Modify the hasSideEffects of MTLR and MFLR from 1 to 0

[qshanz via Phabricator via llvm-commits]

steven.zhang added inline comments.


================
Comment at: llvm/test/CodeGen/PowerPC/ppcf128-constrained-fp-intrinsics.ll:1389
+; PC64LE-NEXT:    ld 29, -48(1) # 8-byte Folded Reload
+; PC64LE-NEXT:    mtlr 0
 ; PC64LE-NEXT:    blr
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jsji wrote:
> This is way to far from `ld 0,16(1)` now. 
But those load in between didn't have any dependency. So, it is likely an heuristic between the resource and latency. 


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https://reviews.llvm.org/D71390