[PATCH] D71515: [AArch64] match fcvtl2 with bitcasted extract

[Sanjay Patel via Phabricator via llvm-commits]

spatel created this revision.
spatel added reviewers: efriedma, aemerson, evandro, sdesmalen, dmgreen.
Herald added subscribers: hiraditya, kristof.beyls, mcrosier.
Herald added a project: LLVM.

I think this is one of the suggestions for eliminating a regression in D63815 <https://reviews.llvm.org/D63815>. If correct, we probably want similar enhancements for half->float extends, but I stopped here to confirm if this is correct.


https://reviews.llvm.org/D71515

Files:
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/test/CodeGen/AArch64/arm64-vcvt_f.ll


Index: llvm/test/CodeGen/AArch64/arm64-vcvt_f.ll
===================================================================
--- llvm/test/CodeGen/AArch64/arm64-vcvt_f.ll
+++ llvm/test/CodeGen/AArch64/arm64-vcvt_f.ll
@@ -39,21 +39,14 @@
 }
 
 define <2 x double> @test_vcvt_high_f64_f32_bitcast(<4 x float> %x) nounwind readnone ssp {
-; GENERIC-LABEL: test_vcvt_high_f64_f32_bitcast:
-; GENERIC:       // %bb.0:
-; GENERIC-NEXT:    ext.16b v0, v0, v0, #8
-; GENERIC-NEXT:    fcvtl v0.2d, v0.2s
-; GENERIC-NEXT:    ret
-;
-; FAST-LABEL: test_vcvt_high_f64_f32_bitcast:
-; FAST:       // %bb.0:
-; FAST-NEXT:    fcvtl2 v0.2d, v0.4s
-; FAST-NEXT:    ret
+; CHECK-LABEL: test_vcvt_high_f64_f32_bitcast:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    fcvtl2 v0.2d, v0.4s
+; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: test_vcvt_high_f64_f32_bitcast:
 ; GISEL:       // %bb.0:
-; GISEL-NEXT:    ext.16b v0, v0, v0, #8
-; GISEL-NEXT:    fcvtl v0.2d, v0.2s
+; GISEL-NEXT:    fcvtl2 v0.2d, v0.4s
 ; GISEL-NEXT:    ret
   %bc1 = bitcast <4 x float> %x to <2 x double>
   %ext = shufflevector <2 x double> %bc1, <2 x double> undef, <1 x i32> <i32 1>
@@ -63,23 +56,14 @@
 }
 
 define <2 x double> @test_vcvt_high_i64_f32_bitcast(<2 x i64> %x) nounwind readnone ssp {
-; GENERIC-LABEL: test_vcvt_high_i64_f32_bitcast:
-; GENERIC:       // %bb.0:
-; GENERIC-NEXT:    ext.16b v0, v0, v0, #8
-; GENERIC-NEXT:    fcvtl v0.2d, v0.2s
-; GENERIC-NEXT:    ret
-;
-; FAST-LABEL: test_vcvt_high_i64_f32_bitcast:
-; FAST:       // %bb.0:
-; FAST-NEXT:    ext.16b v0, v0, v0, #8
-; FAST-NEXT:    // kill: def $d0 killed $d0 killed $q0
-; FAST-NEXT:    fcvtl v0.2d, v0.2s
-; FAST-NEXT:    ret
+; CHECK-LABEL: test_vcvt_high_i64_f32_bitcast:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    fcvtl2 v0.2d, v0.4s
+; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: test_vcvt_high_i64_f32_bitcast:
 ; GISEL:       // %bb.0:
-; GISEL-NEXT:    ext.16b v0, v0, v0, #8
-; GISEL-NEXT:    fcvtl v0.2d, v0.2s
+; GISEL-NEXT:    fcvtl2 v0.2d, v0.4s
 ; GISEL-NEXT:    ret
   %ext = shufflevector <2 x i64> %x, <2 x i64> undef, <1 x i32> <i32 1>
   %bc2 = bitcast <1 x i64> %ext to <2 x float>
Index: llvm/lib/Target/AArch64/AArch64InstrInfo.td
===================================================================
--- llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -3637,6 +3637,9 @@
 def : Pat<(v2f64 (fpextend (v2f32 (extract_subvector (v4f32 V128:$Rn),
                                                     (i64 2))))),
           (FCVTLv4i32 V128:$Rn)>;
+def : Pat<(v2f64 (fpextend (v2f32 (bitconvert (v1i64
+               (extract_subvector (v2i64 V128:$Rn), (i64 1))))))),
+          (FCVTLv4i32 V128:$Rn)>;
 
 def : Pat<(v4f32 (fpextend (v4f16 V64:$Rn))), (FCVTLv4i16 V64:$Rn)>;
 def : Pat<(v4f32 (fpextend (v4f16 (extract_subvector (v8f16 V128:$Rn),


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