[PATCH] D71074: [Aarch64][SVE] Add intrinsics for scatter stores

[Andrzej Warzynski via Phabricator via llvm-commits]

andwar updated this revision to Diff 233816.
andwar marked an inline comment as done.
andwar added a comment.



- add `ImmArg` in the defintion of `AdvSIMD_ScatterStore_VectorBase_Intrinsic`
- duplicated `imm0_31`, `uimm5s2`, `uimm5s4`, `uimm5s8` with `TImmLeaf`-based equivalents (required after adding `ImmArg` above)
- rebased on top of trun
- removed a whitespace


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D71074/new/

https://reviews.llvm.org/D71074

Files:
  llvm/include/llvm/IR/IntrinsicsAArch64.td
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/lib/Target/AArch64/AArch64InstrFormats.td
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/lib/Target/AArch64/SVEInstrFormats.td
  llvm/test/CodeGen/AArch64/sve-intrinsics-scatter-stores-32bit-scaled-offsets.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-scatter-stores-32bit-unscaled-offsets.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-scatter-stores-64bit-scaled-offset.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-scatter-stores-64bit-unscaled-offset.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-scatter-stores-vector-base.ll

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