[PATCH] D71390: [PowerPC] Modify the hasSideEffects of MTLR and MFLR from 1 to 0

[Jinsong Ji via Phabricator via llvm-commits]

jsji requested changes to this revision.
jsji added a subscriber: steven.zhang.
jsji added a comment.
This revision now requires changes to proceed.

@steven.zhang can you work with @ZhangKang to see why, and whether we rely on `hasSideEffects` for a better schedule right now. Thanks.



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Comment at: llvm/test/CodeGen/PowerPC/CSR-fit.ll:32
 ; CHECK-PWR8-NEXT:    ld r14, -144(r1) # 8-byte Folded Reload
+; CHECK-PWR8-NEXT:    mtlr r0
 ; CHECK-PWR8-NEXT:    blr
----------------
I see this is actually causing degradation here.  `mtlr` is 5 cycle instruction, moving them together is not a good idea.



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  https://reviews.llvm.org/D71390/new/

https://reviews.llvm.org/D71390