[PATCH] D71391: [PowerPC] Modify the hasSideEffects of some VSX instructions from 1 to 0

[qshanz via Phabricator via llvm-commits]

steven.zhang added inline comments.


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Comment at: llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1369
 // Vector Extract Unsigned Byte/Halfword/Word Left/Right-Indexed
+let hasSideEffects = 0 in {
 def VEXTUBLX : VX1_RT5_RA5_VB5<1549, "vextublx", []>;
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Jim wrote:
> hasSideEffects = 0 should be added class `VX1_RT5_RA5_VB5`.
> Something like:
> ```
> let hasSideEffects = 0 in
> class VX1_RT5_RA5_VB5<bits<11> xo, string opc, list<dag> pattern>
> ...
> ```
I don't think it is good idea to clear this flag in the format class definition, except we have clear semantics that, there won't be any side effect for all the instructions with this format. But I don't see it, though, for now, it only have six instructions instance.  What do you think ?


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  https://reviews.llvm.org/D71391/new/

https://reviews.llvm.org/D71391