[PATCH] D70812: [Aarch64][SVE] Add DAG combine rules for gather loads and sext/zext

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen accepted this revision.
sdesmalen added a comment.
This revision is now accepted and ready to land.

Aside from two nits, LGTM!



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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:9925
+                                    TargetLowering::DAGCombinerInfo &DCI) {
+  assert(N->getOpcode() == ISD::AND && "Expected ISD::AND");
+  assert(N->getValueType(0).isScalableVector() && "Expected SVE vector");
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nit: Are these asserts necessary?


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:9939
+  // These instructions perform an implicit zero-extend.
+  if ((Opc == AArch64ISD::GLD1) || (Opc == AArch64ISD::GLD1_SCALED) ||
+      (Opc == AArch64ISD::GLD1_SXTW) || (Opc == AArch64ISD::GLD1_SXTW_SCALED) ||
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nit: Can you make this a switch statement with a default that returns `SDValue()`?


Repository:
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  https://reviews.llvm.org/D70812/new/

https://reviews.llvm.org/D70812