[PATCH] D70680: [ARM][Thumb2] Fix ADD/SUB invalid writes to SP

[Diogo N. Sampaio via Phabricator via llvm-commits]

dnsampaio marked 5 inline comments as done.
dnsampaio added inline comments.


================
Comment at: llvm/lib/Target/ARM/ARMInstrThumb2.td:925-938
+    bits<4>  Rn = 13;
+    bits<4>  Rd = 13;
+    bits<12> imm;
+
+    let Inst{31-27} = 0b11110;
+    let Inst{26}    = imm{11};
+    let Inst{25-24} = 0b01;
----------------
dnsampaio wrote:
> john.brawn wrote:
> > This duplicates a lot of what's in T2sTwoRegImm, and also incorrectly forces bit 20 (which encodes the 's' bit) to 0 causing adds to be encoded as add.
> > 
> > I think what should be here is the same as the ri variant, but with "let Rn = 13; let Rd = 13;" at the top.
> Is there a special way to do those let? From the ones I managed to compile, using
> ```
> let Rn = 13 in
> let Rd = 13 in
> def spImm...```
> I kept getting ` error: Duplicate predicate in FastISel table!`. So I reduced as much as possible, fixing not setting the `S` bit (20).
Never-mind, I just did set them inside the definition and it works.


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https://reviews.llvm.org/D70680