[PATCH] D70942: [LegalizeTypes] Bugfixes for big-endian targets when handling BITCASTs

[Mikael Holmén via Phabricator via llvm-commits]

uabelho added a subscriber: eli.friedman.
uabelho added a comment.

In D70942#1773282 <https://reviews.llvm.org/D70942#1773282>, @efriedma wrote:

> LGTM.  (Left some notes on the testcase if anyone else wants to follow.)


Thanks for the analysis @eli.friedman!

If I change the int_to_vec test so it loads from memory instead of passing the i80 as a parameter I get

  define i16 @int_to_vec() {
  ; CHECK-LABEL: int_to_vec:
  ; CHECK:       @ %bb.0:
  ; CHECK-NEXT:    movw r0, :lower16:i80_p
  ; CHECK-NEXT:    movt r0, :upper16:i80_p
  ; CHECK-NEXT:    ldr r1, [r0]
  ; CHECK-NEXT:    ldr r2, [r0, #4]
  ; CHECK-NEXT:    ldrh r0, [r0, #8]
  ; CHECK-NEXT:    orr r0, r0, r2, lsl #16
  ; CHECK-NEXT:    lsl r3, r1, #16
  ; CHECK-NEXT:    orr r2, r3, r2, lsr #16
  ; CHECK-NEXT:    lsr r1, r1, #16
  ; CHECK-NEXT:    b .LBB1_1
  ; CHECK-NEXT:  .LBB1_1: @ %bb.1
  ; CHECK-NEXT:    vmov.i32 q8, #0x0
  ; CHECK-NEXT:    vrev32.16 q8, q8
  ; CHECK-NEXT:    @ kill: def $d16 killed $d16 killed $q8
  ; CHECK-NEXT:    vmov.u16 r0, d16[0]
  ; CHECK-NEXT:    bx lr
    %i80 = load i80, i80* @i80_p, align 1
    br label %bb.1
  
  bb.1:
    %vec = bitcast i80 %i80 to <5 x i16>
    %e0 = extractelement <5 x i16> %vec, i32 0
    ret i16 %e0
  }

without the fix and

  define i16 @int_to_vec() {
  ; CHECK-LABEL: int_to_vec:
  ; CHECK:       @ %bb.0:
  ; CHECK-NEXT:    sub sp, sp, #8
  ; CHECK-NEXT:    movw r0, :lower16:i80_p
  ; CHECK-NEXT:    movt r0, :upper16:i80_p
  ; CHECK-NEXT:    ldr r1, [r0]
  ; CHECK-NEXT:    ldr r2, [r0, #4]
  ; CHECK-NEXT:    ldrh r0, [r0, #8]
  ; CHECK-NEXT:    orr r0, r0, r2, lsl #16
  ; CHECK-NEXT:    lsl r3, r1, #16
  ; CHECK-NEXT:    orr r2, r3, r2, lsr #16
  ; CHECK-NEXT:    lsr r1, r1, #16
  ; CHECK-NEXT:    str r2, [sp, #4] @ 4-byte Spill
  ; CHECK-NEXT:    str r1, [sp] @ 4-byte Spill
  ; CHECK-NEXT:    b .LBB1_1
  ; CHECK-NEXT:  .LBB1_1: @ %bb.1
  ; CHECK-NEXT:    ldr r0, [sp] @ 4-byte Reload
  ; CHECK-NEXT:    lsl r1, r0, #16
  ; CHECK-NEXT:    ldr r2, [sp, #4] @ 4-byte Reload
  ; CHECK-NEXT:    orr r1, r1, r2, lsr #16
  ; CHECK-NEXT:    @ implicit-def: $d16
  ; CHECK-NEXT:    vmov.32 d16[0], r1
  ; CHECK-NEXT:    @ implicit-def: $q9
  ; CHECK-NEXT:    vmov.f64 d18, d16
  ; CHECK-NEXT:    vrev32.16 q9, q9
  ; CHECK-NEXT:    @ kill: def $d18 killed $d18 killed $q9
  ; CHECK-NEXT:    vmov.u16 r0, d18[0]
  ; CHECK-NEXT:    add sp, sp, #8
  ; CHECK-NEXT:    bx lr
    %i80 = load i80, i80* @i80_p, align 1
    br label %bb.1
  
  bb.1:
    %vec = bitcast i80 %i80 to <5 x i16>
    %e0 = extractelement <5 x i16> %vec, i32 0
    ret i16 %e0
  }

with, so at least the fix makes a difference in that case too.
If you prefer that I can update the testcase.

Otherwise I'll just commit as is now.

Thanks!


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D70942/new/

https://reviews.llvm.org/D70942