[PATCH] D70582: [FPEnv][X86] Constrained FCmp intrinsics enabling on X86

Pengfei Wang via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Dec 5 18:44:26 PST 2019


pengfei marked 3 inline comments as done.
pengfei added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:3577
     EVT VT = Node->getValueType(0);
+    SDValue Chain;
     SDValue CC = Node->getOperand(4);
----------------
uweigand wrote:
> I guess this needs an input chain, right?   I think you'll probably have to add a whole new STRICT_FSELECT_CC node to get this right ...
Since we are supporting both signaling and quite STRICT intrinsics, I think there's no need to expand the STRICT version of `SETCC`, `SELECT_CC` and `BR_CC` now.
That's because `setCondCodeAction` doesn't distinguish signaling and quite. Obviously, some CC that is legal in signaling or quite might be not in another.
The only way is customizing them, otherwise falling back to non STRICT node.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:3648
   case ISD::BR_CC: {
+    SDValue Chain;
     Tmp1 = Node->getOperand(0);              // Chain
----------------
uweigand wrote:
> Similarly here, although BR_CC of course already has a chain.
Same as above.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D70582/new/

https://reviews.llvm.org/D70582





More information about the llvm-commits mailing list