[PATCH] D71074: [Aarch64][SVE] Add intrinsics for scatter stores

[Andrzej Warzynski via Phabricator via llvm-commits]

andwar created this revision.
Herald added subscribers: llvm-commits, psnobl, rkruppe, hiraditya, kristof.beyls, tschuett.
Herald added a reviewer: rengolin.
Herald added a reviewer: efriedma.
Herald added a project: LLVM.
andwar added a parent revision: D70812: [Aarch64][SVE] Add DAG combine rules for gather loads and sext/zext.
andwar added a reviewer: sdesmalen.

This patch adds the following SVE intrinsics for scatter stores:

- 64-bit offsets:
  - @llvm.aarch64.sve.st1.scatter (unscaled)
  - @llvm.aarch64.sve.st1.scatter.index (scaled)
- 32-bit unscaled offsets:
  - @llvm.aarch64.sve.st1.scatter.uxtw (zero-extended offset)
  - @llvm.aarch64.sve.st1.scatter.sxtw (sign-extended-offset)
- 32-bit scaled offsets:
  - @llvm.aarch64.sve.st1.scatter.uxtw.index (zero-extended offset)
  - @llvm.aarch64.sve.st1.scatter.sxtw.index (sign-extended offset)
- vector base + immediate:
  - @llvm.aarch64.sve.st1.scatter.imm

NFCs: Move the TableGen classes for gather load intrnisics so that they
are all in one places. Fixed typo in names.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D71074

Files:
  llvm/include/llvm/IR/IntrinsicsAArch64.td
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/lib/Target/AArch64/SVEInstrFormats.td
  llvm/test/CodeGen/AArch64/sve-intrinsics-scatter-stores-32bit-scaled-offsets.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-scatter-stores-32bit-unscaled-offsets.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-scatter-stores-64bit-scaled-offset.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-scatter-stores-64bit-unscaled-offset.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-scatter-stores-vector-base.ll

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