[PATCH] D71046: Support Intel "l" suffixes for x86_64 R8-R15 registers.

[Michael Trent via Phabricator via llvm-commits]

mtrent created this revision.
mtrent added reviewers: ab, pete, hliao.
Herald added a subscriber: hiraditya.
Herald added a project: LLVM.

Intel's 64-bit architecture specifies the low-byte of registers r8-r15 can
be specified using either a "b" suffix ("r8b") or an "l" suffix ("r8l").
This commit adds "l" suffix alternate strings to the r8b - r15b registers,
using TableGen's Register "AltName" mechanism.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D71046

Files:
  llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
  llvm/lib/Target/X86/X86.td
  llvm/lib/Target/X86/X86RegisterInfo.td


Index: llvm/lib/Target/X86/X86RegisterInfo.td
===================================================================
--- llvm/lib/Target/X86/X86RegisterInfo.td
+++ llvm/lib/Target/X86/X86RegisterInfo.td
@@ -12,7 +12,7 @@
 //
 //===----------------------------------------------------------------------===//
 
-class X86Reg<string n, bits<16> Enc, list<Register> subregs = []> : Register<n> {
+class X86Reg<string n, bits<16> Enc, list<Register> subregs = [], list<string> alt = []> : Register<n, alt> {
   let Namespace = "X86";
   let HWEncoding = Enc;
   let SubRegs = subregs;
@@ -66,14 +66,14 @@
 def DIL  : X86Reg<"dil",   7>;
 def BPL  : X86Reg<"bpl",   5>;
 def SPL  : X86Reg<"spl",   4>;
-def R8B  : X86Reg<"r8b",   8>;
-def R9B  : X86Reg<"r9b",   9>;
-def R10B : X86Reg<"r10b", 10>;
-def R11B : X86Reg<"r11b", 11>;
-def R12B : X86Reg<"r12b", 12>;
-def R13B : X86Reg<"r13b", 13>;
-def R14B : X86Reg<"r14b", 14>;
-def R15B : X86Reg<"r15b", 15>;
+def R8B  : X86Reg<"r8b",   8, [], ["r8l"]>;
+def R9B  : X86Reg<"r9b",   9, [], ["r9l"]>;
+def R10B : X86Reg<"r10b", 10, [], ["r10l"]>;
+def R11B : X86Reg<"r11b", 11, [], ["r11l"]>;
+def R12B : X86Reg<"r12b", 12, [], ["r12l"]>;
+def R13B : X86Reg<"r13b", 13, [], ["r13l"]>;
+def R14B : X86Reg<"r14b", 14, [], ["r14l"]>;
+def R15B : X86Reg<"r15b", 15, [], ["r15l"]>;
 }
 
 let isArtificial = 1 in {
Index: llvm/lib/Target/X86/X86.td
===================================================================
--- llvm/lib/Target/X86/X86.td
+++ llvm/lib/Target/X86/X86.td
@@ -1257,6 +1257,10 @@
 // Assembly Parser
 //===----------------------------------------------------------------------===//
 
+def X86AsmParser : AsmParser {
+  let ShouldEmitMatchRegisterAltName = 1;
+}
+
 def ATTAsmParserVariant : AsmParserVariant {
   int Variant = 0;
 
@@ -1301,6 +1305,7 @@
 def X86 : Target {
   // Information about the instructions...
   let InstructionSet = X86InstrInfo;
+  let AssemblyParsers = [X86AsmParser];
   let AssemblyParserVariants = [ATTAsmParserVariant, IntelAsmParserVariant];
   let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];
   let AllowRegisterRenaming = 1;
Index: llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
===================================================================
--- llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -993,6 +993,7 @@
 /// {
 
 static unsigned MatchRegisterName(StringRef Name);
+static unsigned MatchRegisterAltName(StringRef Name);
 
 /// }
 
@@ -1107,10 +1108,14 @@
   }
 
   RegNo = MatchRegisterName(Tok.getString());
+  if (RegNo == 0)
+    RegNo = MatchRegisterAltName(Tok.getString());
 
   // If the match failed, try the register name as lowercase.
   if (RegNo == 0)
     RegNo = MatchRegisterName(Tok.getString().lower());
+  if (RegNo == 0)
+    RegNo = MatchRegisterAltName(Tok.getString().lower());
 
   // The "flags" and "mxcsr" registers cannot be referenced directly.
   // Treat it as an identifier instead.


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