[PATCH] D69956: [AArch64][SVE] Integer reduction instructions pattern/intrinsics.

[Danilo Carvalho Grael via Phabricator via llvm-commits]

dancgr marked 5 inline comments as done.
dancgr added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:10521
+
+  if (DataVT.getVectorElementType().isScalarInteger() && (VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32 || VT == MVT::i64)) {
+    auto bitSize = VT.getSizeInBits();
----------------
sdesmalen wrote:
> nit: >80chars. Please use clang-format before you commit.
Will do. I had ran clang format for ISelLowering, however there were too many changes in other places. I ran clang-format for the part of code that I have changed.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:10522
+  if (DataVT.getVectorElementType().isScalarInteger() && (VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32 || VT == MVT::i64)) {
+    auto bitSize = VT.getSizeInBits();
+
----------------
sdesmalen wrote:
> nit: `BitSize` is not very descriptive. Perhaps because it is used only once, just propagate `VT.getSizeInBits()` into the expression calculating `OutputVT`?
> nit: The first character of variables in this file are capitalized, so this should have been `BitSize`.
Removed bitsize for clarity.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D69956/new/

https://reviews.llvm.org/D69956