[PATCH] D70875: [X86] Model MXCSR for AVX instructions other than AVX512

[LuoYuanke via Phabricator via llvm-commits]

LuoYuanke added inline comments.


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Comment at: llvm/lib/Target/X86/X86InstrSSE.td:7329
 let Predicates = [HasF16C, NoVLX] in {
-  defm VCVTPH2PS  : f16c_ph2ps<VR128, f64mem, WriteCvtPH2PS>;
-  defm VCVTPH2PSY : f16c_ph2ps<VR256, f128mem, WriteCvtPH2PSY>, VEX_L;
+  defm VCVTPH2PS  : f16c_ph2ps<VR128, f64mem, WriteCvtPH2PS>, SIMD_EXC;
+  defm VCVTPH2PSY : f16c_ph2ps<VR256, f128mem, WriteCvtPH2PSY>, VEX_L, SIMD_EXC;
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Is there any exception when convert from half to single float?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D70875/new/

https://reviews.llvm.org/D70875