[PATCH] D69956: [AArch64][SVE] Integer reduction instructions pattern/intrinsics.

[Danilo Carvalho Grael via Phabricator via llvm-commits]

dancgr marked 9 inline comments as done.
dancgr added a comment.

Done all changes suggested by @sdesmalen.  I removed the unnecessary changes to AArch64 patterns, did all of the small details and added nxv2i64 sddv mapping to uaddv.



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Comment at: llvm/test/CodeGen/AArch64/sve-int-reduce-pred.ll:33
+}
+
+define i64 @uaddv_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {
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sdesmalen wrote:
> For the ACLE `saddv_i64` is also needed, can you add this case as well? (it will just map directly to a `uaddv` instruction directly, so that should be a simple change where you call `LowerSVEIntReduction`
For this, I have decided to map it in the SVEInstrFormat pattern instead of the lowering (I added an extra PatternOperator for the uaddv multiclass). Since we don't have custom lowering for SADDV and UADDV (they return i64 FPR128 types so they don't need it).


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  https://reviews.llvm.org/D69956/new/

https://reviews.llvm.org/D69956