[PATCH] D70858: [GlobalISel][RFC] Importing insert/extract vector element patterns

[Petar Avramovic via Phabricator via llvm-commits]

Petar.Avramovic created this revision.
Petar.Avramovic added reviewers: atanasyan, petarj, arsenm, dsanders, rovka, volkan, qcolombet.
Herald added subscribers: llvm-commits, arphaman, jrtc27, hiraditya, kristof.beyls, arichardson, nhaehnle, wdng, jvesely, sdardis.
Herald added a reviewer: rengolin.
Herald added a project: LLVM.

I am trying to import insert/extract vector element isel patterns. The important first question is what to GINodeEquiv ?
Here's prototype that is able to selectimpl some basic insert/extract vector patterns for MIPS:

- Generic vector_insert `def : GINodeEquiv<G_INSERT_VECTOR_ELT, vector_insert>;` is used for both same and different "vector scalar" and "inserted/extracted elt scalar" size
- Generic vector_extract `def : GINodeEquiv<G_EXTRACT_VECTOR_ELT, vector_extract>;` is used only for floating point vector extract (same "vector scalar" and "inserted/extracted elt scalar" size)
- MipsVExtractSExt and MipsVExtractZExt are used for both same and different "vector scalar" and "inserted/extracted elt scalar" size, although same element size for MipsVExtractZExt gets selected like MipsVExtractSExt (the "same 32-bit element size" on 32-bit machine is extending when executed on 64-bit machine, and this type of extending has to be signextending).

@rovka, could neon use generic G_SEXT_EXTRACT_VECTOR_ELT and G_ZEXT_EXTRACT_VECTOR_ELT since it has similar target specific extending vector extract isd nodes? Probably something like this:
def : GINodeEquiv<G_SEXT_EXTRACT_VECTOR_ELT, ARMvgetlanes>;
def : GINodeEquiv<G_ZEXT_EXTRACT_VECTOR_ELT, ARMvgetlaneu>;
They cant't be imported yet because they have SDNodeXForm (like DSubReg_i8_reg) for subindex.

I think that MIPS has to GINodeEquiv globalisel opcodes without the:
"vector scalar size" has to be the same as "inserted/extracted elt scalar size" 
constraint to match patterns from td files.

Is this a right direction or I need to GINodeEquiv something else ?
There are some size constraints in MachineIRBuilder for G_INSERT_VECTOR_ELT and G_EXTRACT_VECTOR_ELT, G_BUILD_VECTOR_TRUNC also exists, but I don't see what are their GINodeEquiv SDAG-nodes.

Some additional information about the implementation:
Combiner for extract vector is copy of zextload/sextload combiner. 
For MIPS imm index for all insert/extract vector element opcodes is iptr, but that is scalar of pointer size, added ScalarOfPtrSizeMatcher.
Importing EXTRACT_SUBREG patterns:
when EXTRACT_SUBREG is in the middle there is a subregister copy to tmp register, added TempSubRegRenderer.
Figuring out classes for constraints of subreg copy operands.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D70858

Files:
  llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
  llvm/include/llvm/CodeGen/GlobalISel/InstructionSelector.h
  llvm/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h
  llvm/include/llvm/Support/TargetOpcodes.def
  llvm/include/llvm/Target/GenericOpcodes.td
  llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
  llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
  llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
  llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
  llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
  llvm/lib/Target/Mips/MipsLegalizerInfo.cpp
  llvm/lib/Target/Mips/MipsMSAInstrInfo.td
  llvm/lib/Target/Mips/MipsPreLegalizerCombiner.cpp
  llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp
  llvm/lib/Target/Mips/MipsRegisterBanks.td
  llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert-vector-elt.mir
  llvm/test/CodeGen/Mips/GlobalISel/instruction-select/extract_vector_elt_imm_index.mir
  llvm/test/CodeGen/Mips/GlobalISel/instruction-select/extract_vector_elt_variable_index.mir
  llvm/test/CodeGen/Mips/GlobalISel/instruction-select/insert_vector_elt_imm_index.mir
  llvm/test/CodeGen/Mips/GlobalISel/instruction-select/insert_vector_elt_variable_index.mir
  llvm/test/CodeGen/Mips/GlobalISel/legalizer/extract_vector_elt_pre_isel.mir
  llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/extract_vector_elt_pre_isel.ll
  llvm/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/extract_vector_elt_pre_isel.mir
  llvm/test/CodeGen/Mips/GlobalISel/regbankselect/extract_vector_elt_pre_isel.mir
  llvm/utils/TableGen/CodeGenRegisters.cpp
  llvm/utils/TableGen/GlobalISelEmitter.cpp

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