[llvm] dcceab1 - [PowerPC] Add new Future CPU for PowerPC in LLVM
Stefan Pintilie via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 27 12:30:56 PST 2019
Author: Stefan Pintilie
Date: 2019-11-27T14:30:06-06:00
New Revision: dcceab1a0ace424ba4877f53c4c69433e53f1f3f
URL: https://github.com/llvm/llvm-project/commit/dcceab1a0ace424ba4877f53c4c69433e53f1f3f
DIFF: https://github.com/llvm/llvm-project/commit/dcceab1a0ace424ba4877f53c4c69433e53f1f3f.diff
LOG: [PowerPC] Add new Future CPU for PowerPC in LLVM
This is a continuation of D70262
The previous patch as listed above added the future CPU in clang. This patch
adds the future CPU in the PowerPC backend. At this point the patch simply
assumes that a future CPU will have the same characteristics as pwr9. Those
characteristics may change with later patches.
Differential Revision: https://reviews.llvm.org/D70333
Added:
llvm/test/CodeGen/PowerPC/check-cpu.ll
Modified:
llvm/lib/Support/Host.cpp
llvm/lib/Target/PowerPC/PPC.td
llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/lib/Target/PowerPC/PPCSubtarget.h
llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Support/Host.cpp b/llvm/lib/Support/Host.cpp
index 7e07b8f7ca26..ef38c1c09413 100644
--- a/llvm/lib/Support/Host.cpp
+++ b/llvm/lib/Support/Host.cpp
@@ -140,6 +140,9 @@ StringRef sys::detail::getHostCPUNameForPowerPC(StringRef ProcCpuinfoContent) {
.Case("POWER8E", "pwr8")
.Case("POWER8NVL", "pwr8")
.Case("POWER9", "pwr9")
+ // FIXME: If we get a simulator or machine with the capabilities of
+ // mcpu=future, we should revisit this and add the name reported by the
+ // simulator/machine.
.Default(generic);
}
diff --git a/llvm/lib/Target/PowerPC/PPC.td b/llvm/lib/Target/PowerPC/PPC.td
index de007d3b8d0b..6fa46f0a7dce 100644
--- a/llvm/lib/Target/PowerPC/PPC.td
+++ b/llvm/lib/Target/PowerPC/PPC.td
@@ -51,6 +51,8 @@ def DirectivePwr6x
def DirectivePwr7: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR7", "">;
def DirectivePwr8: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR8", "">;
def DirectivePwr9: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR9", "">;
+def DirectivePwrFuture
+ : SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR_FUTURE", "">;
def Feature64Bit : SubtargetFeature<"64bit","Has64BitSupport", "true",
"Enable 64-bit instructions">;
@@ -239,6 +241,13 @@ def ProcessorFeatures {
FeatureVectorsUseTwoUnits, FeaturePPCPreRASched, FeaturePPCPostRASched];
list<SubtargetFeature> Power9FeatureList =
!listconcat(Power8FeatureList, Power9SpecificFeatures);
+
+ // For future CPU we assume that all of the existing features from Power 9
+ // still exist.
+ list<SubtargetFeature> FutureSpecificFeatures =
+ [];
+ list<SubtargetFeature> FutureFeatureList =
+ !listconcat(Power9FeatureList, FutureSpecificFeatures);
}
// Note: Future features to add when support is extended to more
@@ -441,6 +450,9 @@ def : ProcessorModel<"pwr6x", G5Model,
def : ProcessorModel<"pwr7", P7Model, ProcessorFeatures.Power7FeatureList>;
def : ProcessorModel<"pwr8", P8Model, ProcessorFeatures.Power8FeatureList>;
def : ProcessorModel<"pwr9", P9Model, ProcessorFeatures.Power9FeatureList>;
+// No scheduler model for future CPU.
+def : ProcessorModel<"future", NoSchedModel,
+ ProcessorFeatures.FutureFeatureList>;
def : Processor<"ppc", G3Itineraries, [Directive32, FeatureHardFloat,
FeatureMFTB]>;
def : Processor<"ppc32", G3Itineraries, [Directive32, FeatureHardFloat,
diff --git a/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp b/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
index 53dbb02bb8e4..33198efb05f8 100644
--- a/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
+++ b/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
@@ -1603,7 +1603,8 @@ void PPCDarwinAsmPrinter::EmitStartOfAsmFile(Module &M) {
// FIXME: why is power8 missing here?
"ppc64",
"ppc64le",
- "power9"
+ "power9",
+ "future"
};
// Get the numerically largest directive.
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 3c59cea7f96e..8730c88f4353 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -1217,6 +1217,7 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
case PPC::DIR_PWR7:
case PPC::DIR_PWR8:
case PPC::DIR_PWR9:
+ case PPC::DIR_PWR_FUTURE:
setPrefLoopAlignment(Align(16));
setPrefFunctionAlignment(Align(16));
break;
@@ -14204,7 +14205,8 @@ Align PPCTargetLowering::getPrefLoopAlignment(MachineLoop *ML) const {
case PPC::DIR_PWR6X:
case PPC::DIR_PWR7:
case PPC::DIR_PWR8:
- case PPC::DIR_PWR9: {
+ case PPC::DIR_PWR9:
+ case PPC::DIR_PWR_FUTURE: {
if (!ML)
break;
@@ -15383,6 +15385,7 @@ SDValue PPCTargetLowering::combineMUL(SDNode *N, DAGCombinerInfo &DCI) const {
// vector 7 2 2
return true;
case PPC::DIR_PWR9:
+ case PPC::DIR_PWR_FUTURE:
// type mul add shl
// scalar 5 2 2
// vector 7 2 2
diff --git a/llvm/lib/Target/PowerPC/PPCSubtarget.h b/llvm/lib/Target/PowerPC/PPCSubtarget.h
index dcf64a5d6f9b..7266d82a08b5 100644
--- a/llvm/lib/Target/PowerPC/PPCSubtarget.h
+++ b/llvm/lib/Target/PowerPC/PPCSubtarget.h
@@ -57,6 +57,7 @@ namespace PPC {
DIR_PWR7,
DIR_PWR8,
DIR_PWR9,
+ DIR_PWR_FUTURE,
DIR_64
};
}
diff --git a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
index 380d71888525..7079498cd815 100644
--- a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
@@ -651,8 +651,9 @@ unsigned PPCTTIImpl::getCacheLineSize() const {
// On P7, P8 or P9 we have a cache line size of 128.
unsigned Directive = ST->getCPUDirective();
+ // Assume that Future CPU has the same cache line size as the others.
if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8 ||
- Directive == PPC::DIR_PWR9)
+ Directive == PPC::DIR_PWR9 || Directive == PPC::DIR_PWR_FUTURE)
return 128;
// On other processors return a default of 64 bytes.
@@ -684,8 +685,9 @@ unsigned PPCTTIImpl::getMaxInterleaveFactor(unsigned VF) {
// For P7 and P8, floating-point instructions have a 6-cycle latency and
// there are two execution units, so unroll by 12x for latency hiding.
// FIXME: the same for P9 as previous gen until POWER9 scheduling is ready
+ // Assume that future is the same as the others.
if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8 ||
- Directive == PPC::DIR_PWR9)
+ Directive == PPC::DIR_PWR9 || Directive == PPC::DIR_PWR_FUTURE)
return 12;
// For most things, modern systems have two execution units (and
diff --git a/llvm/test/CodeGen/PowerPC/check-cpu.ll b/llvm/test/CodeGen/PowerPC/check-cpu.ll
new file mode 100644
index 000000000000..baa39024ebe8
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/check-cpu.ll
@@ -0,0 +1,11 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=future < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=future < %s | FileCheck %s
+
+
+; Test mcpu=future that should be recognized on PowerPC.
+
+; CHECK-NOT: is not a recognized processor for this target
+; CHECK: .text
+
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