[PATCH] D70072: [ARM] Improve codegen of volatile load/store of i64

[Dave Green via Phabricator via llvm-commits]

dmgreen added inline comments.


================
Comment at: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1279
+    int RHSC;
+    if (isScaledConstantInRange(N.getOperand(1), 1 << Shift, -128, 128, RHSC)) {
+      Base = N.getOperand(0);
----------------
efriedma wrote:
> Are you sure this range computation is right?  The range should be multiples of 4 from -1020 to 1020.
It may be worth adding tests for cases that are close to or just over the boundary.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D70072/new/

https://reviews.llvm.org/D70072