[PATCH] D70670: [RISCV] Implement canRealignStack

[Sam Elliott via Phabricator via llvm-commits]

lenary created this revision.
lenary added reviewers: Jim, shiva0217, luismarques.
Herald added subscribers: llvm-commits, apazos, sameer.abuasal, pzheng, s.egerton, benna, psnobl, jocewei, PkmX, rkruppe, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, MaskRay, jrtc27, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, hiraditya.
Herald added a project: LLVM.
lenary added a child revision: D70401: [WIP][RISCV] Implement ilp32e ABI.

The implementation of `RISCVRegisterInfo::canRealignStack` was left out of the
implementation of Stack Realignment in D62007 <https://reviews.llvm.org/D62007>.

I think this is the root cause of the issues we've seen in D70401 <https://reviews.llvm.org/D70401> around the
spilling of fp64 registers in the ILP32E ABI. Applying this patch seems to
solve those issues.

Unfortunately, I think that failure requires spilling a register with a spill
alignment that is larger than the current stack alignment. Until ILP32E has
landed, we have no registers which satisfy these constraints, so no testcases
have changed with this commit (but, we want to land this patche separately to
ILP32E support).


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D70670

Files:
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
  llvm/lib/Target/RISCV/RISCVRegisterInfo.h


Index: llvm/lib/Target/RISCV/RISCVRegisterInfo.h
===================================================================
--- llvm/lib/Target/RISCV/RISCVRegisterInfo.h
+++ llvm/lib/Target/RISCV/RISCVRegisterInfo.h
@@ -43,6 +43,8 @@
 
   Register getFrameRegister(const MachineFunction &MF) const override;
 
+  bool canRealignStack(const MachineFunction &) const override;
+
   bool requiresRegisterScavenging(const MachineFunction &MF) const override {
     return true;
   }
Index: llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
+++ llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
@@ -152,6 +152,23 @@
   return TFI->hasFP(MF) ? RISCV::X8 : RISCV::X2;
 }
 
+bool RISCVRegisterInfo::canRealignStack(const MachineFunction &MF) const {
+  if (!TargetRegisterInfo::canRealignStack(MF))
+    return false;
+
+  // We need the frame pointer (fp) to restore the stack pointer (sp) when
+  // realigning the stack in the epilog.
+  Register FPReg = RISCV::X8;
+
+  // In order to use fp, it must not be reserved by the user.
+  if (MF.getSubtarget<RISCVSubtarget>().isRegisterReservedByUser(FPReg))
+    return false;
+
+  // In order to use fp, we must be able to reserve it.
+  const MachineRegisterInfo *MRI = &MF.getRegInfo();
+  return MRI->canReserveReg(FPReg);
+}
+
 const uint32_t *
 RISCVRegisterInfo::getCallPreservedMask(const MachineFunction & MF,
                                         CallingConv::ID /*CC*/) const {


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